The layout of the printed-circuit board (PCB) is critical to achieve low EMI and stable power-supply operation as well as optimal efficiency. Make the high frequency current loops as small as possible, and follow these guidelines of good layout practices;

• The TPS5516x-Q1 family of devices is a high-frequency switching converter. Because the four switch MOSFETs are integrated, the device should be located at the center of the DC-DC power stage. Separate the power ground and analog ground such that the control circuit can be connected to the relatively quieter analog ground without being contaminated by the noisy power ground. Use the PGND pin, GND pin, and the device PowerPAD as the single-point connection between the analog and power grounds.
• Identify the high-frequency switched AC-current loops. In step-down mode, the AC current loop is along the path of the input capacitor (C_IN), L1 pin, internal buck-switch leg, and PGND pin, and closes at the input capacitor. In step-up mode, the AC current loop is along the path of the output capacitor (C_OUT), L2 pin, internal boost-switch leg, and PGND pin, and closes at the output capacitor. These two AC-current loops are both involved in buck-boost overlap mode.
• Optimize component placement and orientation before routing any traces. Place the input and output filter capacitors, the device, and the power inductor close together such that the AC-current loops are short, direct, and the spatial areas enclosed by the loops are minimized. Make the power flow in a straight path rather than a zigzag path on the board.
• Place the high frequency decoupling ceramic capacitors for the input and output as close as possible to the device with the main input and output ceramic capacitors placed next to the high-frequency capacitors. This placement helps confine the high switching noises within a very small area around the device.
• Place the VREG decoupling capacitor close to the VREG pin because it serves as the supply to the internal low-side MOSFETs drivers. Because the VREG pin receives power from the output rail, the ground lead of the VREG decoupling capacitor should connect directly to the C_OUT ground to improve device noise immunity.
  Note:

  The VREG_Q pin must always connect to the VREG pin. Both pins should have a Kelvin connection to the decoupling capacitor.

• Place the bootstrap capacitors (C_BST1 and C_BST2) close to the device with short and direct traces to connect to the corresponding device pins becuase these capacitors serve as the supplies to the internal high-side MOSFETs drivers
• Place the VOUT_SENSE decoupling capacitor (C_VOSN) close to the device. Give the placement of this capacitor priority over the main output capacitors.
• For TPS55160-Q1 or TPS55162-Q1, place the sense-resistor divider for the output voltage close to the device.
• Use eight to nine via holes with a 0.3 mm diameter in the device PowerPAD to help dissipate heat through the layers of the ground plane. Additional vias holes around the device PowerPAD can further enhance heat dissipation.
• Use at least ten via holes with a 0.3 mm diameter around the input and output capacitors that are connected to ground-plane layers to minimize the PCB impedance for power current flows.