Table 1. Design Parameters

9.2.2.1 Step One: Select the Switching Frequency

Choose the highest switching frequency possible in order to produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which in turn decrease the device performance. The device is capable of operating between 200 kHz and 2 MHz. Select a moderate switching frequency of 1 MHz in order to achieve both a small solution size and a high-efficiency operation. Using Equation 5, R4 is calculates to 180 kΩ. A standard 1%, 182-kΩ resistor is used in the design.

9.2.2.2 Step Two: Select the Output Inductor

The inductor selected must operate across the entire TPS54418A device input voltage range. To calculate the value of the output inductor, use Equation 19. K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, K_IND is normally from 0.1 to 0.3 for the majority of applications.

For this design example, use a K_IND of 0.3 and the inductor value is calculated to be 0.96 μH. For this design, use an inductor with the nearest standard value of 1.0 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be calculated in Equation 21 and Equation 22.

For this design, the RMS inductor current is 4.014 A and the peak inductor current is 4.58 A. The chosen inductor is a TOKO FDV0630-1R0M. It has a RMS current rating of 9.1 A and a saturation current rating of 20.2 A. The current ratings for this exceed the requirement, but the inductor was chosen for small physical size and low series resistance for high efficiency.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.

Equation 19.

Equation 20.

Equation 21.

Equation 22.

9.2.2.3 Step Three: Choose the Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 25 shows the necessary minimum output capacitance.

For this example, the transient load response is specified as a 3% change in V_OUT for a load step from 1 A (50% load) to 2 A (100%).

Using these numbers gives a minimum capacitance of 37 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Equation 26 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where f_SW is the switching frequency, V_RIPPLE is the maximum allowable output voltage ripple, and I_RIPPLE is the inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. Equation 26 yields 5.2  µF.

Equation 25.

Equation 26.

Equation 27 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 27 indicates the ESR should be less than 57 mΩ. In this case, the ESR of the ceramic capacitor is much less than 57 mΩ.

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, two 22-μF, 10-V, X5R ceramic capacitors with 3 mΩ of ESR are used.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple current. Equation 28 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 28 yields 333 mA.

Equation 27.

Equation 28.

9.2.2.4 Step Four: Select the Input Capacitor

The TPS54418A device requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the device. The input ripple current can be calculated using Equation 29.

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreases as the dc bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 30.

Equation 29.

Equation 30.

Using the design example values, I_OUT(max) = 4 A, C_IN = 10 μF, f_SW = 1 MHz, yields an input voltage ripple of 99 mV and a rms input ripple current of 1.96 A.

9.2.2.5 Step Five: Minimum Load DC COMP Voltage

The TPS54418A implements a minimum COMP voltage clamp for improved load-transient response. The COMP voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreases as the peak inductor current decreases. During a severe load-dump event, for instance, the COMP voltage decreases suddenly, falls below the minimum clamp value, then settles to a lower DC value as the control loop compensates for the transient event. During the time when COMP reaches the minimum clamp voltage, turnon of the high-side power switch is inhibited, keeping the low-side power switch on to discharge the output voltage overshoot more quickly.

Proper application circuit design must ensure that the minimum load steady-state COMP voltage is above the +3 sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the steady-state DC level of COMP must be measured at the minimum designed load and at the maximum designed input voltage, then compared to the minimum COMP clamp voltage shown in Figure 22. These conditions give the minimum COMP voltage for a given design. Generally, the COMP voltage and minimum clamp voltage move by about the same amount with temperature. Increasing the minimum load COMP voltage is accomplished by decreasing the output inductor value or the switching frequency used in a given design.

9.2.2.6 Step Six: Choose the Soft-Start Capacitor

The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the device reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The soft-start capacitor value can be calculated using Equation 31. For the example circuit, the soft-start time is not too critical since the output capacitor value is 44 µF which does not require much current to charge to 1.8 V. The example circuit has the soft-start time set to an arbitrary value of 4 ms which requires a 10 nF capacitor. In the device, I_SS is 2 μA and V_REF is 0.8 V. For this application, maintain the soft-start time in the range between 1 ms and 10 ms.

Equation 31.

where

• C_SS is in nF
• I_SS is in µA
• t_SS is in ms
• V_REF is in V

9.2.2.7 Step Seven: Select the Bootstrap Capacitor

A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating.

9.2.2.8 Step Eight: Undervoltage Lockout Threshold

The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54418A. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 3.1 V (V_START). Switching continues until the input voltage falls below 2.8 V (V_STOP).

The programmable UVLO and enable voltages are set using a resistor divider between the VIN pin and GND to the EN pin. Equation 32 and Equation 33 can be used to calculate the resistance values necessary. From Equation 32 and Equation 33, a 48.7 kΩ between the VIN pin and the EN pin and a 32.4-kΩ resistor between the EN pin and GND are required to produce the 3.1-V start voltage and the 2.8-V stop voltage.

Equation 32.

Equation 33.

9.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors

For the example design, 100 kΩ was selected for R6. Using Equation 34, R7 is calculated as 80 kΩ. The nearest standard 1% resistor is 80.6 kΩ.

Equation 34.

9.2.2.9.1 Output Voltage Limitations

Due to the internal design of the TPS54418A there are limitations to the minimum and maximum achievable output voltages. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 35. There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum output voltage is given by Equation 36. These equations represent the results when the power MOSFETs are matched. Refer to SLYT293 for more information.

Equation 35.

where

• V_OUT(min) is the minimum achievable output voltage
• t_ON(min) is the minimum controllable on-time (110 nsec typical)
• f_SW(max) is the maximum switching frequency including tolerance
• V_IN(max) is the maximum input voltage
• I_OUT(min) is the minimum load current
• R_LS(min) is the minimum low-side MOSFET on-resistance. (30 mΩ typical)
• R_DCR is the series resistance of output inductor

Equation 36.

where

• V_OUT(max) is the maximum achievable output voltage
• t_OFF(max) is the maximum, minimum controllable off time (60 ns typical)
• f_SW(max) is the maximum switching frequency including tolerance
• V_IN(min) is the minimum input voltage
• I_OUT(max) is the maximum load current
• R_HS(max) is the maximum high-side MOSFET on-resistance. (70 mΩ max)
• R_DCR is the series resistance of output inductor

9.2.2.10 Step 10: Select Loop Compensation Components

There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54418A. Because the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.

To get started, the modulator pole, f_P(mod), and the esr zero, f_Z1 must be calculated using Equation 37 and Equation 38. For C_OUT, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 39 and Equation 40 to estimate a starting point for the crossover frequency, f_C. For the example design, f_P(mod) is 8.04 kHz and f_Z1 is 2412 kHz. Equation 39 is the geometric mean of the modulator pole and the esr zero and Equation 40 is the mean of modulator pole and the switching frequency. Equation 39 yields 139 kHz and Equation 40 gives 63 kHz. Use the lower value of Equation 39 or Equation 40 as the maximum crossover frequency. For this example, fc is 35 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed).

Equation 37.

Equation 38.

Equation 39.

Equation 40.

The compensation design takes the following steps:

1. Set up the anticipated cross-over frequency. Use Equation 41 to calculate the compensation network’s resistor value. In this example, the anticipated cross-over frequency f_C is 35 kHz. The power stage gain (g_M(ps)) is 13 A/V and the error amplifier gain (g_M(ea)) is 225 µA/V.
Equation 41.
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network’s capacitor can be calculated from Equation 42.
Equation 42.
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it.

From the procedures above, start with a 11.2 kΩ resistor and a 2650 pF capacitor. After prototyping and bode plot measurement, the optimized compensation network selected for this design includes a 7.5 kΩ resistor and a 2700 pF capacitor.

9.2.2.11 Power Dissipation Estimate

Use Equation 43 through Equation 52 to help estimate the device power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the device (P_TOT) includes conduction loss (P_COND), dead time loss (P_D), switching loss (P_SW), gate drive loss (P_GD) and supply current loss (P_Q).

For a given ambient temperature,

For maximum junction temperature (T_J(max) = 150°C)

Additional power can be lost in the regulator circuit due to the inductor ac and dc losses and trace resistance that impact the overall regulator efficiency. Figure 36 and Figure 37 show power dissipation for the EVM.

TA = 25°C

No air flow

Figure 36. Power Dissipation vs Junction Temperature

TJ(max) = 150°C

No air flow

Figure 37. Power Dissipation vs Ambient Temperature