ZHCSFG8A AUGUST   2013  – September 2016 TPS54418A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation and Output Current
      3. 8.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Soft-Start Pin
      9. 8.3.9  Sequencing
      10. 8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 8.3.11 Overcurrent Protection
      12. 8.3.12 Frequency Shift
      13. 8.3.13 Reverse Overcurrent Protection
      14. 8.3.14 Synchronize Using the RT/CLK Pin
      15. 8.3.15 Power Good (PWRGD Pin)
      16. 8.3.16 Overvoltage Transient Protection
      17. 8.3.17 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Small Signal Model for Loop Response
      2. 8.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 8.4.3 Small Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Step One: Select the Switching Frequency
        2. 9.2.2.2  Step Two: Select the Output Inductor
        3. 9.2.2.3  Step Three: Choose the Output Capacitor
        4. 9.2.2.4  Step Four: Select the Input Capacitor
        5. 9.2.2.5  Step Five: Minimum Load DC COMP Voltage
        6. 9.2.2.6  Step Six: Choose the Soft-Start Capacitor
        7. 9.2.2.7  Step Seven: Select the Bootstrap Capacitor
        8. 9.2.2.8  Step Eight: Undervoltage Lockout Threshold
        9. 9.2.2.9  Step Nine: Select Output Voltage and Feedback Resistors
          1. 9.2.2.9.1 Output Voltage Limitations
        10. 9.2.2.10 Step 10: Select Loop Compensation Components
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage EN, PWRGD, VIN –0.3 7 V
RT/CLK –0.3 6
COMP, SS, VSENSE –0.3 3
BOOT VPH+ 8 V
Output voltage BOOT-PH 8 V
PH –0.6 7
PH (10 ns transient) –2 7
Source current EN, RT/CLK 100 µA
Sink current COMP, SS 100 µA
PWRGD 10 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VVIN Input voltage 3 6 V
TJ Operating junction temperature –40 150 °C

7.4 Thermal Information(2)

THERMAL METRIC(1) TPS54418A UNIT
RTE (WQFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 50 °C/W
RθJA Junction-to-ambient thermal resistance (3) 37 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 59.1 °C/W
RθJB Junction-to-board thermal resistance 23.1 °C/W
ψJT Junction-to-top characterization parameter 1.4 °C/W
ψJB Junction-to-board characterization parameter 23.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.9 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
(3) Test Board Conditions:
  • 2 inches × 2 inches, 4 layers, thickness: 0.062 inch
  • 2 oz. copper traces located on the top of the PCB
  • 2 oz. copper ground planes located on the two internal layers and bottom layer
  • 4 thermal vias (10 mil) located under the device package

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ 150°C, 2.95 ≤ VVIN ≤ 6 V (unless otherwise noted) over operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN)
VVIN Operating input voltage 2.95 6 V
VUVLO Internal under voltage lockout threshold No voltage hysteresis, rising and falling 2.6 2.8 V
IQ(vin) Shutdown supply current VEN = 0 V, TA = 25°C, 2.95 V ≤ VVIN ≤ 6 V 2 5 μA
Iq Quiescent current VVSENSE = 0.9 V, VVIN = 5 V, 25°C,
RT = 400 kΩ		 350 500 μA
ENABLE AND UVLO (EN)
VTH(en) Enable threshold Rising 1.16 1.25 1.37 V
Falling 1.18
IEN Input current Enable rising threshold + 50 mV –3.2 μA
Enable falling threshold – 50 mV –0.65
VOLTAGE REFERENCE (VSENSE)
VREF Voltage reference 2.95 V ≤ VVIN ≤ 6 V, –40°C <TJ < 150°C 0.795 0.803 0.811 V
MOSFET
RDS(HFET) High-side switch resistance (VBOOT – VPH) = 5 V 30 60 mΩ
(VBOOT – VPH) = 2.95 V 44 70
RDS(LFET) Low-side switch resistance VVIN = 5 V 30 60 mΩ
VVIN = 2.95 V 44 70
ERROR AMPLIFIER
IIN Input current 7 nA
gM(ea) Error amplifier transconductance –2 μA < ICOMP < 2 μA, VCOMP = 1 V 225 μS
gm(EA,ss) Error amplifier transconductance during soft-start –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 70 μS
ICOMP Error amplifier source/sink VCOMP = 1 V, 100 mV overdrive ±20 μA
gM COMP to ISWITCH transconductance 13 A/V
CURRENT LIMIT
ILIM Current limit threshold Instantaneous peak current 5.0 6.4 A
THERMAL SHUTDOWN
TSD Thermal Shutdown 175 °C
TSD(hyst) Hysteresis 15 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)
fSW Switching frequency range using RT mode 200 2000 kHz
fSW Switching frequency RRT = 400 kΩ 400 500 600 kHz
fSW Switching frequency range using CLK mode 300 2000 kHz
tMIN(CLK) Minimum CLK pulse width 75 ns
VRT/CLK RT/CLK voltage RRT/CLK = 400 kΩ 0.5 V
VIH(CLK) RT/CLK high threshold 1.6 2.2 V
VIL(CLK) RT/CLK low threshold 0.4 0.6 V
tDLY RT/CLK falling edge to PH rising edge delay fSW = 500 kHz with RRT resistor in series 90 ns
tLOCK(PLL) PLL lock-in time fSW = 500 kHz 14 μs
HIGH-SIDE POWER MOSFET (PH)
tON(min) Minimum on time Measured at 50% points on PH, IOUT = 4 60 ns
Measured at 50% points on PH, VVIN = 5 V,
IOUT = 0 A		 110
tOFF(min) Minimum off time Prior to skipping off pulses,
(VBOOT – VPH) = 2.95 V, IOUT = 4		 60 ns
tRISE Rise time VVIN = 5 V 1.5 V/ns
tFALL Fall time VVIN = 5 V 1.5 V/ns
BOOT (BOOT)
RBOOT BOOT charge resistance VVIN = 5 V 16 Ω
VUVLO(Boot) BOOT-PH UVLO VVIN = 2.95 V 2.1 V
SOFT-START (SS )
ICHG Charge current VSS = 0.4 V 1.8 μA
VSSxREF SS to reference crossover 98% nominal 0.9 V
VDSCHG(SS) SS discharge voltage (overload) VVSENSE = 0 V 20 μA
IDSCHG(SS) SS discharge current (UVLO, EN, thermal fault) VVIN = 5 V, VSS = 0.5 V 1.25 mA
POWER GOOD (PWRGD)
VTH(PG) VSENSE threshold VVSENSE falling (fault) 91% VREF
VVSENSE rising (good) 93%
VVSENSE rising (fault) 107%
VVSENSE falling (Good) 105%
VHYST(PG) Hysteresis VVSENSE falling 2%
IPH(lkg) Output high leakage VVSENSE = VREF, VPWRGD = 5.5 V 2 nA
RPG Power Good on-resistance 100 Ω
VOL Low-level output voltage IPWRGD = 3.5 mA 0.3 V
VMIN(PG) Minimum input voltage for valid output VPWRGD < 0.5 V , IOUT = 100 μA 1.2 1.6 V

7.6 Typical Characteristics

TPS54418A hilo_rdson_lvs946.gif
Figure 1. High-Side and Low-Side On-Resistance vs Junction Temperature
TPS54418A hi_cur_tj_lvs946.gif
Figure 3. High-Side Current Limit vs Junction Temperature
TPS54418A fs_rt_lvs946.gif
Figure 5. Switching Frequency vs RT Resistance Low Frequency Range
TPS54418A fs_vsense.gif
Figure 7. Switching Frequency vs Vsense
TPS54418A ea2_tj_lvs946.gif
Figure 9. Transconductance (Soft-Start) vs Junction Temperature
TPS54418A pin_cur_tj_lvs946.gif
Figure 11. Pin Current vs Junction Temperature
TPS54418A ss_tj_lvs946.gif
Figure 13. Charge Current vs Junction Temperature
TPS54418A vin_tj_lvs946.gif
Figure 15. Input Voltage vs Junction Temperature
TPS54418A shutdwn_vi_lvs946.gif
Figure 17. Shutdown Supply Current vs Input Voltage
TPS54418A icc_vi_lvs946.gif
Figure 19. Supply Current vs Input Voltage
TPS54418A radson_tj_lvs946.gif
Figure 21. PWRGD On Resistance vs Junction Temperature
TPS54418A freq_temp_lvs946.gif
Figure 2. Frequency vs Junction Temperature
TPS54418A vref_tj_lvs946.gif
Figure 4. Voltage Reference vs Junction Temperature
TPS54418A fs2_rt_lvs946.gif
Figure 6. Switching Frequency vs RT Resistance High Frequency Range
TPS54418A ea_tj_lvs946.gif
Figure 8. Transconductance vs Junction Temperature
TPS54418A en_tj_lvs946.gif
Figure 10. Enable Pin Voltage vs Junction Temperature
TPS54418A pin2_cur_tj_lvs946.gif
Figure 12. Pin Current vs Junction Temperature
TPS54418A ss2_tj_lvs946.gif
Figure 14. Discharge Current vs Junction Temperature
TPS54418A shutdwn_tj_lvs946.gif
Figure 16. Shutdown Supply Current vs Junction Temperature
TPS54418A icc_tj_lvs946.gif
Figure 18. Supply Current vs Junction Temperature
TPS54418A pwrgd_tj_lvs946.gif
Figure 20. PWRGD Threshold vs Junction Temperature
TPS54418A comp_v_temp_slvs946.gif
Figure 22. Comp Voltage Clamp vs Junction Temperature