ZHCSDN8 March   2015 TPS51275B-1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 典型应用图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PWM Operations
      2. 8.3.2  Adaptive On-Time and PWM Frequency Control
      3. 8.3.3  Light-Load Condition in Out-of-Audio Operation
      4. 8.3.4  Enable and Power Good
      5. 8.3.5  Soft-Start and Discharge
      6. 8.3.6  VREG5 and VREG3 Linear Regulators
      7. 8.3.7  VCLK for Charge Pump
      8. 8.3.8  Overcurrent Protection
      9. 8.3.9  Output Overvoltage and Undervoltage Protection
      10. 8.3.10 Undervoltage Lockout Protection
      11. 8.3.11 Over-Temperature Protection (OTP)
    4. 8.4 Device Functional Modes
      1. 8.4.1 D-CAP Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Components Selection
          1. 9.2.2.1.1 Step 1. Determine the Value of R1 and R2
          2. 9.2.2.1.2 Step 2. Select the Inductor
          3. 9.2.2.1.3 Step 3. Select Output Capacitors
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Routing (Sensitive Analog Portion)
      3. 11.1.3 Routing (Power portion)
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

Good layout is essential for stable power-supply operation. Follow these guidelines for an efficient PCB layout.

11.1.1 Placement

  • Place voltage setting resistors close to the device pins.
  • Place bypass capacitors for the VREG5 and VREG3 regulators close to the device pins.

11.1.2 Routing (Sensitive Analog Portion)

  • Use small copper space for the VFBx pins. Short and narrow traces are available to avoid noise coupling.
  • Connect the VFB resistor trace to the positive node of the output capacitor. Routing the inner layer away from power traces is recommended.
  • Use short and wide trace from the VFB resistor to vias to GND (internal GND plane).

11.1.3 Routing (Power portion)

  • Use wider and shorter traces of the DRVLx pin for the low-side gate drivers to reduce stray inductance.
  • Use the parallel traces of the SWx and DRVHx pins for the high-side MOSFET gate drive in a same layer or on adjoin layers, and keep these traces away from the DRVLx pin.
  • Use wider and shorter traces between the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET
  • The thermal pad is the GND terminal of this device. Five or more vias with 0.33-mm (13-mils) diameter connected from the thermal pad to the internal GND plane should be used to have strong GND connection and help heat dissipation.

11.2 Layout Example

TPS51275B-1 layout_slvsct3.gifFigure 26. TPS51275B-Q1 Layout Example