ZHCSQN0 December   2023 TPS4800-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

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7.3.3 Short-Circuit Protection

The TPS48000-Q1 feature adjustable short circuit protection. The threshold and response time can be adjusted using RISCP resistor and CTMR capacitor respectively. The device senses the voltage across CS+ and CS– pins. These pins can be connected across the FET drain and source terminals for FET RDSON sensing or across an external high and low side current sense resistor (RSNS) as shown in Figure 7-5, Figure 7-6, , Figure 7-7 and Figure 7-8 respectively.

GUID-20230517-SS0I-Z0PN-P0TV-LBQDGT4Z3NFQ-low.svgFigure 7-5 TPS48000-Q1 Application Circuit With External Sense Resistor RSNS Based High Side Current Sensing
GUID-20230517-SS0I-BCCW-JQWL-HQ1KSNCXP3BQ-low.svgFigure 7-6 TPS48000-Q1 Application Circuit With MOSFET RDSON Based Current Sensing
GUID-20231114-SS0I-QTTD-KJZZ-VWBKN27GQPD8-low.svgFigure 7-7 TPS48000-Q1 Application Circuit With External Sense Resistor RSNS Based Low Side Current Sensing on Battery Side
GUID-20230517-SS0I-KVNP-DDFT-JRKCG66QQMXD-low.svgFigure 7-8 TPS48000-Q1 Application Circuit With External Sense Resistor RSNS Based Low Side Current Sensing

Set the short-circuit detection threshold using an external RISCP resistor across ISCP and GND pins. Use Equation 5 to calculate the required RISCP value:

Equation 5. RISCP (Ω)= ISC×RSNS - 10 mV2 μA

Refer to Equation 9 in Section 8.1.1 section for update in equation in final revision of IC.

Where,

RSNS is the high or low side current sense resistor value or the FET RDSON value.

ISC is the desired short circuit current level.

The short circuit protection response is fastest with no CTMR cap connected across TMR and GND pins.

With device powered ON and EN/UVLO, INP pulled high, During Q1 turn ON, first VGS of external FET is sensed by monitoring the voltage across PD to SRC. Once PD to SRC voltage raises above V(G_GOOD) (7.5 V typical) threshold which ensures that the external FET is enhanced, then the SCP comparator output is monitored. If the sensed voltage across CS+ and CS– exceeds the short-circuit set point (VSCP), PD pulls low to SRC and FLT asserts low. Subsequent events can be set either to be auto-retry or latch off as described in following sections.

VGS of external FET (Q1) is only monitored when CS_SEL is pulled low. VGS of external FET (Q1) is not monitored for low side current sensing as shown in Figure 7-7 and Figure 7-8.