ZHCSD47E December   2014  – October 2022 TPD2E2U06-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 AEC-Q101 Qualified
      2. 7.3.2 IEC 61000-4-2 Level 4
      3. 7.3.3 IO Capacitance
      4. 7.3.4 DC Breakdown Voltage
      5. 7.3.5 Ultra-Low Leakage Current
      6. 7.3.6 Low ESD Clamping Voltage
      7. 7.3.7 Industrial Temperature Range
      8. 7.3.8 Small Easy-to-Route Packages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V
VCLAMP IO to GND IPP = 1 A, TLP(1)(3) 9.7 V
IPP = 5 A, TLP(1)(3) 12.4
VCLAMP GND to IO IPP = 1 A, TLP(1)(3) 1.9 V
IPP = 5 A, TLP(1)(3) 4
RDYN Dynamic resistance IO to GND(2)(3) 0.6 Ω
GND to IO(2)(3) 0.4
CL Line capacitance f = 1 MHz, VBIAS = 2.5 V(3) 1.5 1.9 pF
CCROSS Channel-to-channel input capacitance Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V, between channel pins(3) 0.02 0.03 pF
∆CL Variation of channel input capacitance Pin 3 = 0 V, f = 1 MHz, VBIAS = 2.5 V,
Pin 1 to GND – Pin 2 to GND(3)		 0.03 0.1 pF
VBR Break-down voltage IIO = 1 mA(3) 6.5 8.5 V
ILEAK Leakage current VIO = 2.5 V 1 10 nA
(1) Transmission Line Pulse with 10-ns rise time, 100-ns width.
(2) Extraction of RDYN Using least squares fit of TLP characteristics between I = 20 A and I = 30 A.
(3) Measured at 25°C.