ZHCSSN8 july   2023 TMUXHS221LV

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  High-Speed Performance Parameters
    7. 6.7  Switching Characteristics
    8. 6.8  Typical Characteristics – S-Parameters
    9. 6.9  Typical Characteristics – RON
    10. 6.10 Typical Characteristics – Eye Diagrams
    11.     18
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
      2. 7.3.2 Data Line Biasing
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Routing Debug Signals to USB Port
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Systems Examples
        1. 8.2.2.1 PCIe Clock Muxing
        2. 8.2.2.2 USB-C SBU Muxing
        3. 8.2.2.3 Switching USB Port
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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6.5 Electrical Characteristics

over operating free-air temperature and supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Device active current OEn = L 10 17 µA
ISTDN Device shutdown current OEn = H 0.5 3 µA
CON Output ON capacitance to GND OEn = L 1.4 pF
RON Channel ON resistance VI/O = 0 V , IO = –8 mA 3 5.4 Ω
VI/O = 2.4 V, IO = –8 mA 3.9 8 Ω
RON,FLAT Channel ON resistance flatness defined as difference of RON over input voltage range VI/O = 0 V and VI/O = 2.4 V; IO = –8 mA 1 Ω
ΔRON On-resistance match between pairs for the same channel at same VI/O, VCC and TA,  VI/O = 0 V; IO = –8 mA 0.2 Ω
VI/O = 2.4 V; IO = –8 mA 0.2 Ω
VIH Input high voltage, control pins (OEn, SEL) 0.9 3.6 V
VIL Input low voltage, control pins (OEn, SEL) -0.3 0.25
IIH,IN Input high current, control pins (OEn, SEL) VIN = 3.6 V 8 µA
IIL,IN Input low current, control pins (OEn, SEL) VIN = 0 V 0.2 µA
II/O,H Input high current, data pins (Dx, DAx, DBx) VI/O = 3.6 V 5 µA
II/O,L Input low current, data pins (Dx, DAx, DBx) VI/O = 0 V 0.2 µA
IHIZ,I/O Leakage current through turned off switch OEn = H; VI/O = 3.6 V 8 µA
IOFF,IN Failsafe leakage current for control pins (IN) VCC = 0 V, VIN = 1.98 V 12 µA
IOFF,I/O Failsafe leakage current for data pins (I/O) VCC = 0 V, VI/O = 3.6 V 12 µA