4 Revision History
Changes from July 22, 2021 to August 27, 2021 (from Revision I (July 2021) to Revision J (August 2021))
-
通篇:删除了引用的“DMIPS”Go
- (Device Comparison): Deleted "MCU Island with Lockstep Arm
Cortex-R5Fs" row, as info in Lockstep and Safety Targeted rows. Go
- (Pin Attributes): Updated Buffer Types for MCU_PORz and PORz to FS
ResetGo
- Updated USB0/1_RCALIB note to indicate the pin must be connected
with an external resistor to VSS even when unused.Go
- Updated REXT pin note to show it should always be connected through
an external resistor to VSS, even when unusedGo
- Added clarification notes to MMC1_SDCD and MMC2_SDCD signals about
pulled down requirementGo
- Updated CSI0 Signal Descriptions and CSI1 Signal
Descriptions to show the RCALIB pins must be connected to VSS through
the external resistor even when unused.Go
- (DSI_TX0 Signal Descriptions): Updated RCALIB pin description to show
the pin must be connected to VSS through an external resistor even when
unused.Go
- Added note indicting power balls should be connected to voltage
specified in Recommended Operating Conditions when
unusedGo
- Added SERDES[0:4]_REXT rows in Connections for Unused Pins,
these pins need to be connected to VSS when unusedGo
- Showed VMON balls should be connected to PWR if unused in
Connections for Unused Pins. Also added note specifying MMC1_SDCD and
MMC2_SDCD should be pulled down to function properly Go
- Showed CSI[1:0]_RXRCALIB, DSI_TXRCALIB, USB[1:0]_RCALIB pins should
be connected to VSS is unused in Connections for Unused
Pins
Go
- Updated Specifications and removed note saying specifications
are preliminaryGo
- (Speed Grade Maximum Frequency): Updated/Changed LPDDR4 frequency
for L and E speed grades from "4266" and "3733" MT/s to "3733" and
"3200" MT/s, respectivelyGo
- (Electrical Characteristics tables): Added FS Reset Electrical
Characteristics TableGo
- (SERDES Electrical Characteristics): Added SERDES REFCLK electrical
characteristics table; the limits are only applicable when internal termination
is enabled. Added compliance notes to industrial specs related to USB, SGMII,
QSGMII, UFS, DP, eDP, and LPDDR4. Go
- (GPMC and NOR Flash — Sync Burst Read — 4x16–bit): Updated figure for
GPMC_WAIT[j] signal (F21, F22)Go
- (GPMC and Multiplexed NOR Flash — Sync Burst Write): Updated figure for
GPMC_WAIT[j] signal (F21, F22)Go
- (McSPI): Updated output load limit for SPI_CLK.Go
- (Timing and Switching Characteristics): Updated MMC1, MMC2 SDR12, SDR25,
SDR50, SDR104 switching characteristics parameters to show data is launched off of rising
edgeGo
- (OSPI Switching Characteristics Table - Data
Training): Updated cycle time for CLK to 6 ns (1.8 V) from
6.02 ns and 7.5 ns (3.3 V) from 7.52 ns for both SDR and
DDR.Go
- (OSPI Switching Characteristics - No Data Training SDR Mode ):
Updated 3.3 V cycle time to 7.5 ns from 7.52 ns.Go
Changes from July 19, 2021 to July 21, 2021 (from Revision H (July 2021) to Revision I (July 2021))
- (Nomenclature Description): Added device type "P" and
"R"Go
Changes from April 1, 2021 to July 19, 2021 (from Revision G (April 2021) to Revision H (July 2021))
- (特性):添加了用以阐明部分器件型号上的器件安全与安防/ASIL 的声明Go
- 更新了“说明”部分Go
- (功能方框图):更新了图像Go
- (Device Comparison): Removed XJ721EGALF from table note 7 to make
the note generic. Added rows and footnotes clarifying certain safety and
security feature are available on select part number variantsGo
- (Related Products): Updated link and description for Software
Development KitGo
- (Pin Attributes): Added the secondary pin multiplexing functions for
the SERDES and controlled by CTRLMMR regsGo
- (CPSW2G): Added a Note with a reference to the CPTS Signal
Descriptions table, as part of the SubsystemGo
- (Signal Descriptions): Added note to clarify CPTS signal
connectionGo
- (Signal Descriptions): Moved MCU CPTS signals from CPSW2G to CPTS
section. Moved SYNCn_OUT signals from SYSTEM to CPTS section. Updated both sets
of signal descriptions.Go
- Updated description for
VDDA_ADC0/1 to reference internal tie to VREFPGo
- Added note indicting power balls should be connected to voltage
specified in Recommended Operating Conditions when
unusedGo
- (Pin Multiplexing): Updated PADCONFIG address column to show actual address
values instead of offset valuesGo
- (Abs Max Ratings): Added Latch-Up Performance parameter
valuesGo
- (Recommended Operating Conditions): Updated min voltage limit for
VDDS_DDR rails to 1.06 V. Updated description for VDD_CPU AVS Range Go
- (Speed Grade Maximum Frequency): Updated/Changed E speed grade,
increasing R5FSS0/1 from "750MHz" to "1000MHz"Go
- (MLB Electrical Characteristics table): Updated IOL/IOH=6 mA;
VILSS=0.3*VDDIO; VIH=0.75*VDDIO. Added slew rate informationGo
- (Electrical Characteristics tables): Updated eMMC PHY VILSS, VIHSS,
VOL, VOH, IOL, IOH limits.Go
- (Electrical Characteristics tables): Update ADC leakage for VSS to
show negative currentGo
- (Electrical Characteristics tables): Removed HFOSC/LFOSC leakage
current parameter. Removed I2C slew rate parameter. Removed SDIO and LVCMOS slew
rate.Go
- Removed leakage current parameter for VPP_CORE,
VPP_MCUGo
- Updated Power Supply Sequencing SectionGo
- (Input and Output Clocks / Oscillators):Updated "Input Clocks
Interface" imageGo
- (WKUP_OSC0 Crystal Electrical Characteristics): Updated/Changed
Cshunt, ESRxtal = 80 Ω from "24MHz" to now "25
MHz"Go
- (OSC1 Crystal Electrical Characteristics): Updated/Changed
Cshunt, ESRxtal = 80 Ω from "24MHz" to now "25
MHz"Go
- Added WKUP_LFOSC0 startup
time limiGo
- (Device Module Clock Frequencies): Renamed title and added references
to TRM/DM sections describing module clock and frequencies.Go
- (ATCLK[x] Switching Characteristics):
Updated/Changed table information and associated ATCLK[x]
Timing figure.Go
- Updated CSI-2 max freq supportGo
- (GPMC): Added IOSET information for GPMC0 signalsGo
- (I3C): Updated parameter names from "D#" to "OD#" and updated images
new names and corected/deleted some timings.Go
- (McASP Timing Conditions): Updated td(Trace Delay) parameter
limitsGo
- (McSPI): Added IOSET information for MCU_SPI0 and
MCU_SPI1.Go
- (MMC1/2 - SD/SDIO Interface): Added UHS-I SDR104 support as well as
corresponding Timing Switching CharacteristicsGo
- Added note clarifying I/O timing is not applicable when OSPI is used
with data training Go
- (OSPI DDR Timing): Removed internal loopback and internal pad
loopback mode limits from OSPI timing tablesGo
- (Detailed Description): Added power supply description and described
how common power supply types can be grouped.Go
- (External Oscillator): Added reference to Clock Specifications
section.Go
- (20210706): Updated Reset section descriptionGo
- (LPDDR4 Board Design and Layout Guidelines): Updated ulink and title to be
Jacinto 7 LPDDR guidelinesGo
- (Nomenclature Description): Removed XJ721EGALF from table note 4 to
make the note genericGo