SLLSE81A March   2011  – March 2016 SN75LVCP600S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Equalization
      2. 8.3.2 Auto Low-Power (ALP) Mode (see )
      3. 8.3.3 Out-Of-Band (OOB) Support
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage (2) VCC –0.5 4 V
Voltage Differential I/O –0.5 4 V
Control I/O –0.5 VCC + 0.5 V
Continuous power dissipation See Thermal Information Table
Storage temperature, TA –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±9000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine model (MM) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

typical values for all parameters are at VCC = 3.3 V and TA = 25°C; all temperature limits are specified by design
PARAMETER MIN NOM MAX UNITS
VCC Supply voltage 3 3.3 3.6 V
CCOUPLING Coupling capacitor 12 nF
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) SN75LVCP600S UNIT
DSK (SON)
10 PINS
RθJA Junction-to-ambient thermal resistance 55.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.9 °C/W
RθJB Junction-to-board thermal resistance 29.2 °C/W
ψJT Junction-to-top characterization parameter 1.0 °C/W
ψJB Junction-to-board characterization parameter 29.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 9.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE PARAMETERS
ICCMax Active mode supply current MODE/EQ/DE/SQ_TH = NC, K28.5 pattern at 6 Gbps,
VID = 700 mVpp, (SATA mode)		 29 41 mA
MODE/EQ/DE/SQ_TH = VCC, K28.5 pattern at 6 Gbps,
VID = 700 mVpp, (SAS mode)		 32 45
ICCPS Auto power-save mode ICC When auto low-power conditions are met 3.3 5 mA
Maximum data rate 6 Gbps
OOB
VOOB_SAS Input OOB threshold (output squelched below this level) f = 750MHz; SQ_TH=0, MODE = 1,
measured at receiver pin 		88 112 131 mVpp
f = 750MHz; SQ_TH=1, MODE = 1,
measured at receiver pin 		67 85 100
VOOB_SATA Input OOB threshold (output squelched below this level) f = 750MHz; SQ_TH=0, MODE = 0,
measured at receiver pin 		40 66 86
f = 750MHz; SQ_TH=1, MODE = 0,
measured at receiver pin 		35 56 72
DVdiffOOB OOB differential delta 25 mV
DVCMOOB OOB common-mode delta 50 mV
CONTROL LOGIC
VIH High-level input voltage For all control pins 1.4 V
VIL Low-level input voltage 0.5 V
VINHYS Input hysteresis 115 mV
IIH High-level input current MODE, SQ_TH = VCC 30 μA
EQ, DE = VCC 20
IIL Low-level input current MODE, SQ_TH = GND –30
EQ, DE = GND –10
RECEIVER AC/DC
ZDIFFRX Differential input impedance 85 100 115 Ω
ZSERX Single-ended input impedance 40 Ω
VCMRX Common-mode voltage 1.7 V
RLDiffRX Differential mode return loss (RL) f = 150 MHz–300 MHz 18 26 dB
f = 300 MHz–600 MHz 14 23
f = 600 MHz–1.2 GHz 10 17
f = 1.2 GHz–2.4 GHz 8 14
f = 2.4 GHz–3 GHz 3 13
RXDiffRLSlope Differential mode RL slope f = 300 MHz–6 GHz –13 dB/dec
RLCMRX Common-mode return loss f = 150 MHz–300 MHz 5 10 dB
f = 300 MHz–600 MHz 5 18
f = 600 MHz–1.2 GHz 2 16
f = 1.2 GHz–2.4 GHz 1 12
f = 2.4 GHz–3 GHz 1 12
VdiffRX Differential input voltage PP MODE = 1, f = 1.5 GHz and 3 GHz 275 1600 mVpp
MODE = 0, f = 1.5 GHz and 3 GHz 225 1600
IBRX Impedance balance f = 150 MHz–300 MHz 30 47 dB
f = 300 MHz–600 MHz 30 40
f = 600 MHz–1.2 GHz 20 34
f = 1.2 GHz–2.4 GHz 10 28
f = 2.4 GHz–3. GHz 10 24
f = 3 GHz–5 GHz 4 22
f = 5 GHz–6.5 GHz 4 22
TRANSMITTER AC/DC
ZdiffTX Pair differential impedance 85 100 122 Ω
ZSETX Single-ended input impedance 40 Ω
VTXtrans Sequencing transient voltage Transient voltages on the serial data bus during power sequencing (lab load) –1.2 0 1.2 V
RLDiffTX Differential mode return loss f = 150 MHz–300 MHz 13 22 dB
f = 300 MHz–600 MHz 8 21
f = 600 MHz–1.2 GHz 6 20
f = 1.2 GHz–2.4 GHz 6 17
f = 2.4 GHz–3 GHz 3 17
TXDiffRLSlope Differential-mode RL slope f = 300 MHz–3 GHz –13 dB/dec
RLCMTX Common-mode return loss f = 150 MHz–300 MHz 5 19 dB
f = 300 MHz–600 MHz 5 16
f = 600 MHz–1.2 GHz 2 11
f = 1.2 GHz–2.4 GHz 1 9
f = 2.4 GHz–3 GHz 1 10
IBTX Impedance balance f = 150 MHz–300 MHz 30 43 dB
f = 300 MHz–600 MHz 30 40
f = 600 MHz–1.2 GHz 20 32
f = 1.2 GHz–2.4 GHz 10 25
f = 2.4 GHz–3 GHz 10 27
f = 3 GHz–5 GHz 4 25
f = 5. GHz–6.5 GHz 4 26
DiffVppTX Differential output-voltage swing DE = 1, MODE = 1→(SAS), f = 3 GHz
(under no interconnect loss)		 385 850 1300 mVpp
DE = 0, MODE = 0→(SATA), f = 3 GHz
(under no interconnect loss)		 400 600 800
DE De-emphasis level DE = 1 –1.3 dB
DE = 0 0
VCMAC_TX TX AC CM voltage At 1.5 GHz 20 50 mVpp
At 3 GHz 11 26 dBmv
(rms)
At 6 GHz 13 30
VCMTX Common-mode voltage 1.7 V
TxR/Flmb TX rise/fall imbalance At 3 Gbps 3% 18%
TxAmplmb TX amplitude imbalance 1.5% 10%
TRANSMITTER JITTER AT CP(1)
3-Gbps SATA Mode
TJTX Total jitter(1) 0.26 0.38 UIpp
DJTX Deterministic jitter VID = 500 mVpp, UI = 333 ps, K28.5 control character, EQ/DE = 1 0.13 0.24 UIpp
RJTX Residual random jitter VID = 500 mVpp, UI = 333 ps, K28.7 control character, EQ/DE = 1 1.16 1.95 ps-rms
6-Gbps SATA Mode
TJTX Total jitter(1) 0.37 0.61 UIpp
DJTX Deterministic jitter VID = 500 mVpp, UI = 167 ps, K28.5 control character, EQ/DE = 1 0.12 0.32 UIpp
RJTX Residual random jitter VID = 500 mVpp, UI = 167 ps, K28.7 control character, EQ/DE = 1 1.15 2.2 ps-rms
3-Gbps SAS Mode
TJTX Total jitter(1) 0.25 0.37 UIpp
DJTX Deterministic jitter VID = 500 mVpp, UI = 333 ps, K28.5 control character, EQ/DE = 1 0.12 0.23 UIpp
RJTX Residual random jitter VID = 500 mVpp, UI = 333 ps, K28.7 control character, EQ/DE = 1 1.11 2 ps-rms
6-Gbps SAS Mode
TJTX Total jitter(1) 0.35 0.57 UIpp
DJTX Deterministic jitter VID = 500 mVpp, UI = 167 ps, K28.5 control character, EQ/DE = 1 0.10 0.29 UIpp
RJTX Residual random jitter VID = 500 mVpp, UI = 167 ps, K28.7 control character, EQ/DE = 1 1.1 2.14 ps-rms
(1) TJ = (14.1 × RJSD + DJ), where RJSD is one standard deviation value of RJ Gaussian distribution. Jitter measurement is at the CP connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown in Figure 1.

6.6 Timing Requirements

MIN NOM MAX UNIT
DEVICE PARAMETERS
tPDelay Propagation delay Measured using K28.5 pattern, See Figure 3 280 330 ps
AutoLPENTRY Auto low power entry time Electrical idle at input, See Figure 5 11 20 μs
AutoLPEXIT Auto low power exit time After first signal activity, See Figure 5 30 40 ns
OOB
tOOB1 OOB mode enter See Figure 4 3 8 ns
tOOB2 OOB mode exit See Figure 4 3 8 ns
RECEIVER AC/DC
t20-80RX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. SATA/SAS 6 Gbps speed measured 1 inch (2.54 cm) from device pin 62 75 ps
tskewRX Differential skew Difference between the single-ended mid-point of the RX+ signal rising/falling edge, and the single-ended mid-point of the RX– signal falling/rising edge 30 ps
TRANSMITTER AC/DC
t20-80TX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. At 6 Gbps SATA or SAS, under no load, measured at the pin 33 50 76 ps
tskewTX Differential skew Difference between the single-ended mid-point of the TX+ signal rising/falling edge, and the single-ended mid-point of the TX– signal falling/rising edge, SATA or SAS mode 4 14 ps
SN75LVCP600S jitter_tst_llse63.gif Figure 1. Jitter Measurement Test Condition
SN75LVCP600S tx_rx_loss_llse63.gif Figure 2. TX, RX Differential Return Loss Limits
SN75LVCP600S delay_tim_lls912.gif Figure 3. Propagation Delay Timing Diagram
SN75LVCP600S exit_tim_llse81.gif Figure 4. OOB Enter and Exit Timing
SN75LVCP600S auto_low_pwr_llse81.gif Figure 5. Auto Low-Power Mode Entry and Exit Timing

6.7 Typical Characteristics

SN75LVCP600S G001_LLSE81.gif Figure 6. SATA-Mode Deterministic Jitter vs Data Rate
SN75LVCP600S G003_LLSE81.gif Figure 8. SAS-Mode Deterministic Jitter vs Data Rate
SN75LVCP600S G002_LLSE81.gif Figure 7. SATA-Mode Deterministic Jitter vs Launch Amplitude
SN75LVCP600S G004_LLSE81.gif Figure 9. SAS-Mode Deterministic Jitter vs Launch Amplitude