ZHCSK05D July   2019  – October 2022 SN3257-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Characteristics
    7. 6.7 Timing Requirements
    8.     Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  IPOFF Leakage Current
    5. 7.5  Transition Time
    6. 7.6  tON (EN) and tOFF (EN) Time
    7. 7.7  tON (VDD) and tOFF (VDD) Time
    8. 7.8  Break-Before-Make Delay
    9. 7.9  Propagation Delay
    10. 7.10 Skew
    11. 7.11 Charge Injection
    12. 7.12 Capacitance
    13. 7.13 Off Isolation
    14. 7.14 Channel-to-Channel Crosstalk
    15. 7.15 Bandwidth
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Beyond Supply Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Powered-off Protection
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Integrated Pull-Down Resistors
    4. 8.4 Device Functional Modes
      1. 8.4.1 Truth Tables
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

Fail-Safe Logic

The SN3257-Q1 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the select pins of the SN3257-Q1 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature enables operation of the SN3257-Q1 with VDD = 1.5 V while allowing the select pins to interface with a logic level of another device up to 5.5 V.