ZHCSK05D July 2019 – October 2022 SN3257-Q1
PRODUCTION DATA
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB) and drain (Dx) pins of the device. When the enable pin is pulled high, all switches are turned off. When the enable pin is pulled low, the select pin controls the signal path selection. The select pin (SEL) controls the state of all four channels of the SN3257-Q1 and determines which source pin is connected to the drain pins. When the select pin is pulled low, the SxA pin conducts to the corresponding Dx pins. When the select pin is pulled high, the SxB pin conducts to the corresponding Dx pins. The SN3257-Q1 logic pins have internal weak pull-down resistors (6 MΩ) to GND so that it powers-on in a known state.
The SN3257-Q1 can be operated without any external components except for the supply decoupling capacitors. Unused logic control pins should be tied to GND or VDD to ensure the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (SxA, SxB, or Dx) should be connected to GND.