SNVS256D Novmeber   2003  – November 2016 LP3943

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface (SCL and SDA Pins) Timing Requirements
    7. 6.7 Typical Characteristic
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 I2C Data Validity
      2. 7.5.2 I2C START and STOP Conditions
      3. 7.5.3 Transferring Data
      4. 7.5.4 Auto Increment
    6. 7.6 Register Maps
      1. 7.6.1 Binary Format for Input Registers (Read-only)—Address 0x00 and 0x01
      2. 7.6.2 Binary Format for Frequency Prescaler and PWM Registers — Address 0x02 to 0x05
      3. 7.6.3 Binary Format for Selector Registers — Address 0x06 to 0x09
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reducing IQ When LEDs are OFF
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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9 Power Supply Recommendations

The LP3943 is designed to be powered from a 2.3-V minimum to a 5.5-V maximum supply input.