7.5.1 I²C Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW.

Figure 2. I²C Data Validity

7.5.2 I²C START and STOP Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits. The I²C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 3. I²C START and STOP Conditions

7.5.3 Transferring Data

Every byte put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received.

After the START condition, a chip address is sent by the I²C master. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3943 hardwires bits 7 to 4 and leaves bits 3 to 1 selectable, as shown in Figure 4. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The LP3943 supports only a WRITE during chip addressing. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.

Figure 4. Chip Address Byte

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled LOW by either master or slave)

rs = repeated start

xx = 60 to 67

Figure 5. LP3943 Register Write

However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure 6.

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled LOW by either master or slave)

rs = repeated start

xx = 60 to 67

Figure 6. LP3943 Register Read

7.5.4 Auto Increment

Auto increment is a special feature supported by the LP3943 to eliminate repeated chip and register addressing when data are to be written to or read from registers in sequential order. The auto increment bit is inside the register address byte, as shown in Figure 7. Auto increment is enabled when this bit is programmed to “1” and disabled when it is programmed to “0”.

Bits 5, 6 and 7 in the register address byte must always be zero.

Figure 7. Register Address Byte

In the READ mode, when auto increment is enabled, I²C master could receive any number of bytes from LP3943 without selecting chip address and register address again. Every time the I²C master reads a register, the LP3943 increments the register address, and the next data register is read. When I²C master reaches the last register (09H), the register address rolls over to 00H.

In the WRITE mode, when auto increment is enabled, the LP3943 increments the register address every time I²C master writes to register. When the last register (09H register) is reached, the register address rolls over to 02H, not 00H, because the first two registers in LP3943 are read-only registers. It is possible to write to the first two registers independently, and the LP3943 device will acknowledge, but the data is ignored.

If auto increment is disabled, and the I²C master does not change register address, it continues to write data into the same register.

Figure 8. Programming With Auto Increment Disabled (in WRITE Mode)

Figure 9. Programming With Auto Increment Enabled (in WRITE Mode)

Table 1. LP3943 Register Table

7.6.1 Binary Format for Input Registers (Read-only)—Address 0x00 and 0x01

7.6.2 Binary Format for Frequency Prescaler and PWM Registers — Address 0x02 to 0x05

7.6.3 Binary Format for Selector Registers — Address 0x06 to 0x09

Programming Example:

• Dim LEDs 0 to 7 at 1 Hz at 25% duty cycle
• Dim LEDs 8 to 12 at 5 Hz at 50% duty cycle
• Set LEDs 13, 14 and 15 off
• Step 1: Set PSC0 to achieve DIM0 of 1 s
• Step 2: Set PWM0 duty cycle to 25%
• Step 3: Set PSC1 to achieve DIM1 of 0.2 s
• Step 4: Set PWM1 duty cycle to 50%
• Step 5: Set LEDs 13, 14 and 15 off by loading the data into LS3 register
• Step 6: Set LEDs 0 to 7 to point to DIM0
• Step 7: Set LEDs 8 to 12 to point to DIM1