SNVS337F June   2006  – September 2015 LP38859

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Voltage
      2. 6.3.2 Bias Voltage
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Supply Sequencing
      5. 6.3.5 Reverse Voltage
      6. 6.3.6 Soft-Start
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation with 3 V ≤ VBIAS ≤ 5.5 V, VOUT(TARGET)+ 0.3 V ≤ VIN ≤ VBIAS
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Capacitors
          1. 7.2.2.1.1 Output Capacitor
          2. 7.2.2.1.2 Input Capacitor
          3. 7.2.2.1.3 Bias Capacitor
        2. 7.2.2.2 Power Dissipation and Heat-Sinking
      3. 7.2.3 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Community Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Layout

9.1 Layout Guidelines

The dynamic performance of the LP38859 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP38859. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP38859, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP38859 ground pin using as wide and short of a copper trace as is practical.

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP38859 using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND pins. The regulator ground pin must be connected to the external circuit ground so that the regulator and its capacitors have a single-point ground.

Stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the LP38859 device and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and its capacitors fixed the problem.

Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors.

9.2 Layout Example

LP38859 layoutex_TO-263.gif Figure 27. LP38859 Layout Example