SNVS522I August   2007  – August 2015 LP38501-ADJ , LP38503-ADJ

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Stability and Phase Margin
      2. 7.3.2 Load Transient Response
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Reverse Current Path
      5. 7.3.5 Short-Circuit Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Operation (LP38501-ADJ Only)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Setting The Output Voltage
        5. 8.2.2.5 RFI/EMI Susceptibility
        6. 8.2.2.6 Output Noise
        7. 8.2.2.7 Power Dissipation/Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
IN pin voltage (survival) −0.3 6 V
EN pin voltage (survival) −0.3 6 V
OUT pin voltage (survival) −0.3 6 V
IOUT (survival) Internally limited
Power dissipation(2) Internally limited
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). See Application and Implementation.

6.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
Input supply voltage 2.7 5.5 V
Enable input voltage 0 5.5 V
Output current (DC) 0 3 A
VOUT 0.6 5 V
Junction temperature(2) −40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Operating junction temperature must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (RθJA). See Application and Implementation.

6.4 Thermal Information

THERMAL METRIC(1) LP38501 and LP38503 UNIT
KTT(DDPAK/TO-263) NDQ (TO-263)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 41.8 33.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.0 22.1 °C/W
RθJB Junction-to-board thermal resistance 24.8 16.9 °C/W
ψJT Junction-to-top characterization parameter 13.1 5.8 °C/W
ψJB Junction-to-board characterization parameter 23.8 16.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 2.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise specified VIN = 3.3 V, IOUT = 10 mA, CIN = 10 μF, COUT = 10 μF, VEN = VIN, VOUT = 1.8 V. Minimum and maximum limits apply over the junction temperature (TJ) range of –40°C to +125°C and are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VADJ ADJ pin voltage(1) 2.7 V ≤ VIN ≤ 5.5 V
10 mA ≤ IOUT ≤ 3 A
TJ = 25°C		 0.584 0.605 0.626 V
2.7 V ≤ VIN ≤ 5.5 V
10 mA ≤ IOUT ≤ 3 A		 0.575 0.635
VADJ ADJ pin voltage (A grade)(1) 2.7 V ≤ VIN ≤ 5.5 V
10 mA ≤ IOUT ≤ 3 A
TJ = 25°C		 0.596 0.605 0.614 V
2.7 V ≤ VIN ≤ 5.5 V
10 mA ≤ IOUT ≤ 3 A		 0.587 0.623
IADJ ADJ pin bias current 2.7 V ≤ VIN ≤ 5.5 V
TJ = 25°C		 50 nA
2.7 V ≤ VIN ≤ 5.5 V 750 nA
VDO Dropout voltage(2) IOUT = 3 A
TJ = 25°C		 420 550 mV
IOUT = 3 A 665 mV
ΔVOUT / ΔVIN Output voltage line regulation(1)(3) 2.7 V ≤ VIN ≤ 5.5 V
TJ = 25°C		 0.04 %/V
2.7 V ≤ VIN ≤ 5.5 V 0.05
ΔVOUT / ΔIOUT Output voltage load regulation(1)(4) 10 mA < IOUT < 3 A
TJ = 25°C		 0.12 %/A
10 mA < IOUT < 3 A 0.24
IGND Ground pin current in normal operation mode 10 mA < IOUT < 3 A
TJ = 25°C		 2 4 mA
10 mA < IOUT < 1.5 A 5
IDISABLED Ground pin current VEN < VIL(EN), TJ = 25°C 0.025 0.125 µA
VEN < VIL(EN) 15
IOUT(PK)GND Peak output current VOUT ≥ VOUT(NOM) – 5% 6 A
ISC Short-circuit current VOUT = 0 V 6 A
VOUT = 0 V, TJ = 25°C 3.5
ENABLE INPUT (LP38501 Only)
VIH(EN) Enable logic high VOUT = ON 1.4 V
VIL(EN) Enable logic low VOUT = OFF 0.65
td(off) Turnoff delay Time from VEN < VIL(EN) to VOUT = OFF
ILOAD = 3 A		 25 µs
td(on) Turnon delay Time from VEN > VIH(EN) to VOUT = ON
ILOAD = 3 A		 25 µs
IIH(EN) Enable pin high current VEN = VIN 35 nA
IIL(EN) Enable pin low current VEN = 0 V 35
AC PARAMETERS
PSRR Ripple rejection VIN = 3 V, IOUT = 3 A, ƒ = 120 Hz 58 dB
VIN = 3 V, IOUT = 3 A, ƒ = 1 kHz 56
ρn(l/f) Output noise density ƒ = 120 Hz, COUT = 10 µF CER 1 µV/√Hz
en Output noise voltage BW = 100 Hz – 100 kHz
COUT = 10 µF CER		 100 µV(RMS)
THERMALS
TSD Thermal shutdown TJ rising 170 — °C
ΔTSD Thermal shutdown hysteresis TJ falling from TSD 10 — °C
(1) The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the adjust voltage tolerance specification.
(2) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. For any output voltage less than 2.5 V, the minimum VIN operating voltage is the limiting factor.
(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.
(4) Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in the load current.

6.6 Typical Characteristics

Unless otherwise specified: TJ = 25°C, VIN = 2.7 V, VEN = VIN, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA, VOUT = 1.8 V.
LP38501-ADJ LP38503-ADJ 30036110.png
Figure 1. Noise Density
LP38501-ADJ LP38503-ADJ 30028111.png
Figure 3. IGND vs Load Current
LP38501-ADJ LP38503-ADJ 30036113.png
Figure 5. VADJ vs Temperature
LP38501-ADJ LP38503-ADJ 30036116.png
Figure 7. VEN vs Temperature
LP38501-ADJ LP38503-ADJ 30028118.png
Figure 9. Load Regulation vs Temperature
LP38501-ADJ LP38503-ADJ 30036114.png
Figure 2. Noise Density
LP38501-ADJ LP38503-ADJ 30036112.png
Figure 4. IGND(OFF) vs Temperature
LP38501-ADJ LP38503-ADJ 30028115.png
Figure 6. Dropout Voltage vs Load Current
LP38501-ADJ LP38503-ADJ 30036117.png
Figure 8. Turnon Characteristics
LP38501-ADJ LP38503-ADJ 30036120.png
Figure 10. PSRR