SNVS522I August   2007  – August 2015 LP38501-ADJ , LP38503-ADJ

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Stability and Phase Margin
      2. 7.3.2 Load Transient Response
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Reverse Current Path
      5. 7.3.5 Short-Circuit Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Operation (LP38501-ADJ Only)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Setting The Output Voltage
        5. 8.2.2.5 RFI/EMI Susceptibility
        6. 8.2.2.6 Output Noise
        7. 8.2.2.7 Power Dissipation/Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

Good layout practices minimize voltage error and prevent instability which can result from ground loops. The input and output capacitors must be directly connected to the device pins with short traces that have no other current flowing in them (Kelvin connect).

The best way to do this is to place the capacitors very near the device and make connections directly to the device pins via short traces on the top layer of the PCB. The regulator ground pin must be connected through vias to the internal or backside ground plane so that the regulator has a single point ground.

The external resistors which set the output voltage must also be located very near the device with all connections directly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to the load point or DC error could be induced.

10.2 Layout Examples

LP38501-ADJ LP38503-ADJ 38502_layout_snvs539.gifFigure 29. LP38501-ADJ TO-263 Layout
LP38501-ADJ LP38503-ADJ 38500_layout_snvs539.gifFigure 30. LP38503-ADJ TO-263 Layout