ZHCSU09H July   2004  – December 2023 LP2981 , LP2981A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
      6. 6.3.6 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
        1. 7.1.1.1 Recommended Capacitors for the Legacy Chip
          1. 7.1.1.1.1 Tantalum Capacitors
          2. 7.1.1.1.2 Ceramic Capacitors
          3. 7.1.1.1.3 Aluminum Capacitors
        2. 7.1.1.2 Recommended Capacitors for the New Chip
      2. 7.1.2 Input and Output Capacitor Requirements
        1. 7.1.2.1 Input Capacitor
        2. 7.1.2.2 Output Capacitor
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON and OFF Input Operation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1.2.2 Output Capacitor

For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-6).

For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the LP2981 具有关断功能的 100mA 超低压降稳压器 LP2981 采用 SOT-23 封装的 100mA 低压降稳压器 LP2981 采用 SOT-23 封装的 100mA 低压降稳压器 特性 特性 应用 应用 说明 说明 Table of Contents Table of Contents Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description Output Enable Output Enable Dropout Voltage Dropout Voltage Current Limit Current Limit Undervoltage Lockout (UVLO) Undervoltage Lockout (UVLO) Thermal Shutdown Thermal Shutdown Output Pulldown Output Pulldown Device Functional Modes Device Functional Modes Device Functional Mode Comparison Device Functional Mode Comparison Normal Operation Normal Operation Dropout Operation Dropout Operation Disabled Disabled Application and Implementation Application and Implementation Application Information Application Information Recommended Capacitor Types Recommended Capacitor Types Recommended Capacitors for the Legacy Chip Recommended Capacitors for the Legacy Chip Tantalum Capacitors Tantalum Capacitors Ceramic Capacitors Ceramic Capacitors Aluminum Capacitors Aluminum Capacitors Recommended Capacitors for the New Chip Recommended Capacitors for the New Chip Input and Output Capacitor Requirements Input and Output Capacitor Requirements Input Capacitor Input Capacitor Output Capacitor Output Capacitor Estimating Junction Temperature Estimating Junction Temperature Power Dissipation (PD) Power Dissipation (PD) Reverse Current Reverse Current Typical Application Typical Application Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure ON and OFF Input Operation ON and OFF Input Operation Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support Device Nomenclature Device Nomenclature Documentation Support Documentation Support Related Documentation Related Documentation Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates 支持资源 支持资源 Trademarks Trademarks 静电放电警告 静电放电警告 术语表 术语表 Revision History Revision History Revision History Revision History Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information 重要声明和免责声明 重要声明和免责声明 LP2981 采用 SOT-23 封装的 100mA 低压降稳压器 LP2981 采用 SOT-23 封装的 100mA 低压降稳压器 特性 G 添加了器件信息 表、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 yes H 更新了整个文档中的表格、图和交叉参考的编号格式 yes H 更改了整个文档，以便与当前系列格式保持一致 yes H 向文档添加了 M3 器件 yes 输入电压 (VIN) 范围： 旧芯片：2.2V 至 16V 新芯片：2.5V 至 16V 输出电压 (VOUT) 范围：1.2V 至 5.0V 输出电压 (VOUT) 精度： A 级旧芯片为 ±0.75% 标准级旧芯片为 ±1.25% 新芯片 ±0.5%（A 级和标准级） 负载和温度范围内的输出电压 (VOUT) 精度: ±1%（新芯片） 输出电流：高达 100mA 低 IQ（新芯片）：ILOAD = 0mA 时为 69μA 低 IQ（新芯片）：ILOAD = 100mA 时为 620μA 关断电流与温度间的关系： < 1μA（旧芯片） ≤ 1.75μA（新芯片） 输出电流限制和热保护 使用 2.2µF 陶瓷电容器实现稳定工作（新芯片） 高 PSRR（新芯片）： 1kHz 频率下为 75dB，1MHz 频率下为 45dB 工作结温：–40°C 至 125°C 封装：5 引脚 SOT-23 (DBV) 特性 G 添加了器件信息 表、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 yes H 更新了整个文档中的表格、图和交叉参考的编号格式 yes H 更改了整个文档，以便与当前系列格式保持一致 yes H 向文档添加了 M3 器件 yes G 添加了器件信息 表、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 yes H 更新了整个文档中的表格、图和交叉参考的编号格式 yes H 更改了整个文档，以便与当前系列格式保持一致 yes H 向文档添加了 M3 器件 yes G 添加了器件信息 表、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 yes G添加了器件信息 表、ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分器件信息ESD 等级特性说明器件功能模式应用和实施电源相关建议布局器件和文档支持机械、封装和可订购信息yes H 更新了整个文档中的表格、图和交叉参考的编号格式 yes H更新了整个文档中的表格、图和交叉参考的编号格式yes H 更改了整个文档，以便与当前系列格式保持一致 yes H更改了整个文档，以便与当前系列格式保持一致yes H 向文档添加了 M3 器件 yes H向文档添加了 M3 器件yes 输入电压 (VIN) 范围： 旧芯片：2.2V 至 16V 新芯片：2.5V 至 16V 输出电压 (VOUT) 范围：1.2V 至 5.0V 输出电压 (VOUT) 精度： A 级旧芯片为 ±0.75% 标准级旧芯片为 ±1.25% 新芯片 ±0.5%（A 级和标准级） 负载和温度范围内的输出电压 (VOUT) 精度: ±1%（新芯片） 输出电流：高达 100mA 低 IQ（新芯片）：ILOAD = 0mA 时为 69μA 低 IQ（新芯片）：ILOAD = 100mA 时为 620μA 关断电流与温度间的关系： < 1μA（旧芯片） ≤ 1.75μA（新芯片） 输出电流限制和热保护 使用 2.2µF 陶瓷电容器实现稳定工作（新芯片） 高 PSRR（新芯片）： 1kHz 频率下为 75dB，1MHz 频率下为 45dB 工作结温：–40°C 至 125°C 封装：5 引脚 SOT-23 (DBV) 输入电压 (VIN) 范围： 旧芯片：2.2V 至 16V 新芯片：2.5V 至 16V 输出电压 (VOUT) 范围：1.2V 至 5.0V 输出电压 (VOUT) 精度： A 级旧芯片为 ±0.75% 标准级旧芯片为 ±1.25% 新芯片 ±0.5%（A 级和标准级） 负载和温度范围内的输出电压 (VOUT) 精度: ±1%（新芯片） 输出电流：高达 100mA 低 IQ（新芯片）：ILOAD = 0mA 时为 69μA 低 IQ（新芯片）：ILOAD = 100mA 时为 620μA 关断电流与温度间的关系： < 1μA（旧芯片） ≤ 1.75μA（新芯片） 输出电流限制和热保护 使用 2.2µF 陶瓷电容器实现稳定工作（新芯片） 高 PSRR（新芯片）： 1kHz 频率下为 75dB，1MHz 频率下为 45dB 工作结温：–40°C 至 125°C 封装：5 引脚 SOT-23 (DBV) 输入电压 (VIN) 范围： 旧芯片：2.2V 至 16V 新芯片：2.5V 至 16V 输出电压 (VOUT) 范围：1.2V 至 5.0V 输出电压 (VOUT) 精度： A 级旧芯片为 ±0.75% 标准级旧芯片为 ±1.25% 新芯片 ±0.5%（A 级和标准级） 负载和温度范围内的输出电压 (VOUT) 精度: ±1%（新芯片） 输出电流：高达 100mA 低 IQ（新芯片）：ILOAD = 0mA 时为 69μA 低 IQ（新芯片）：ILOAD = 100mA 时为 620μA 关断电流与温度间的关系： < 1μA（旧芯片） ≤ 1.75μA（新芯片） 输出电流限制和热保护 使用 2.2µF 陶瓷电容器实现稳定工作（新芯片） 高 PSRR（新芯片）： 1kHz 频率下为 75dB，1MHz 频率下为 45dB 工作结温：–40°C 至 125°C 封装：5 引脚 SOT-23 (DBV) 输入电压 (VIN) 范围： 旧芯片：2.2V 至 16V 新芯片：2.5V 至 16V IN 旧芯片：2.2V 至 16V 新芯片：2.5V 至 16V 旧芯片：2.2V 至 16V新芯片：2.5V 至 16V输出电压 (VOUT) 范围：1.2V 至 5.0VOUT输出电压 (VOUT) 精度： A 级旧芯片为 ±0.75% 标准级旧芯片为 ±1.25% 新芯片 ±0.5%（A 级和标准级） OUT A 级旧芯片为 ±0.75% 标准级旧芯片为 ±1.25% 新芯片 ±0.5%（A 级和标准级） A 级旧芯片为 ±0.75%标准级旧芯片为 ±1.25%新芯片 ±0.5%（A 级和标准级）负载和温度范围内的输出电压 (VOUT) 精度: ±1%（新芯片）OUT输出电流：高达 100mA低 IQ（新芯片）：ILOAD = 0mA 时为 69μAQLOAD低 IQ（新芯片）：ILOAD = 100mA 时为 620μAQLOAD关断电流与温度间的关系： < 1μA（旧芯片） ≤ 1.75μA（新芯片） < 1μA（旧芯片） ≤ 1.75μA（新芯片） < 1μA（旧芯片）≤ 1.75μA（新芯片）输出电流限制和热保护使用 2.2µF 陶瓷电容器实现稳定工作（新芯片）高 PSRR（新芯片）： 1kHz 频率下为 75dB，1MHz 频率下为 45dB 1kHz 频率下为 75dB，1MHz 频率下为 45dB 1kHz 频率下为 75dB，1MHz 频率下为 45dB工作结温：–40°C 至 125°C封装：5 引脚 SOT-23 (DBV) 应用 电表 微型逆变器 服务器 PSU（12V 输出） 家用断路器 单轴和多轴伺服驱动器 应用 电表 微型逆变器 服务器 PSU（12V 输出） 家用断路器 单轴和多轴伺服驱动器 电表 微型逆变器 服务器 PSU（12V 输出） 家用断路器 单轴和多轴伺服驱动器 电表 微型逆变器 服务器 PSU（12V 输出） 家用断路器 单轴和多轴伺服驱动器 电表 电表 微型逆变器 微型逆变器 服务器 PSU（12V 输出） 服务器 PSU（12V 输出） 家用断路器 家用断路器 单轴和多轴伺服驱动器 单轴和多轴伺服驱动器 说明 LP2981 是一款固定输出、低压降 (LDO) 稳压器，支持 2.5V 至 16V 的输入电压范围（仅限新芯片）和高达 100mA 的负载电流。LP2981 支持 1.2V 至 5.0V 的输出范围（新芯片）。 此外，LP2981（新芯片）在整个负载和温度范围内具有 1% 的输出精度，可满足低压微控制器 (MCU) 和处理器的需求。 在该新芯片中，高带宽 PSRR 性能在 1kHz 时为 75dB，在 1MHz 时为 45dB，因此有助于衰减上游直流/直流转换器的开关频率，并尽可能地减少后置稳压器滤波。 内部软启动时间和电流限制保护可减小启动期间的浪涌电流，从而尽可能降低输入电容。还包括标准保护特性，例如过流和过热保护。 封装信息 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981A 有关详细信息，请参阅 。 封装尺寸（长 x 宽）为标称值，并包括引脚（如适用）。 典型应用电路 压降电压与温度间的关系（新芯片） 说明 LP2981 是一款固定输出、低压降 (LDO) 稳压器，支持 2.5V 至 16V 的输入电压范围（仅限新芯片）和高达 100mA 的负载电流。LP2981 支持 1.2V 至 5.0V 的输出范围（新芯片）。 此外，LP2981（新芯片）在整个负载和温度范围内具有 1% 的输出精度，可满足低压微控制器 (MCU) 和处理器的需求。 在该新芯片中，高带宽 PSRR 性能在 1kHz 时为 75dB，在 1MHz 时为 45dB，因此有助于衰减上游直流/直流转换器的开关频率，并尽可能地减少后置稳压器滤波。 内部软启动时间和电流限制保护可减小启动期间的浪涌电流，从而尽可能降低输入电容。还包括标准保护特性，例如过流和过热保护。 封装信息 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981A 有关详细信息，请参阅 。 封装尺寸（长 x 宽）为标称值，并包括引脚（如适用）。 典型应用电路 压降电压与温度间的关系（新芯片） LP2981 是一款固定输出、低压降 (LDO) 稳压器，支持 2.5V 至 16V 的输入电压范围（仅限新芯片）和高达 100mA 的负载电流。LP2981 支持 1.2V 至 5.0V 的输出范围（新芯片）。 此外，LP2981（新芯片）在整个负载和温度范围内具有 1% 的输出精度，可满足低压微控制器 (MCU) 和处理器的需求。 在该新芯片中，高带宽 PSRR 性能在 1kHz 时为 75dB，在 1MHz 时为 45dB，因此有助于衰减上游直流/直流转换器的开关频率，并尽可能地减少后置稳压器滤波。 内部软启动时间和电流限制保护可减小启动期间的浪涌电流，从而尽可能降低输入电容。还包括标准保护特性，例如过流和过热保护。 封装信息 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981A 有关详细信息，请参阅 。 封装尺寸（长 x 宽）为标称值，并包括引脚（如适用）。 LP2981 是一款固定输出、低压降 (LDO) 稳压器，支持 2.5V 至 16V 的输入电压范围（仅限新芯片）和高达 100mA 的负载电流。LP2981 支持 1.2V 至 5.0V 的输出范围（新芯片）。此外，LP2981（新芯片）在整个负载和温度范围内具有 1% 的输出精度，可满足低压微控制器 (MCU) 和处理器的需求。在该新芯片中，高带宽 PSRR 性能在 1kHz 时为 75dB，在 1MHz 时为 45dB，因此有助于衰减上游直流/直流转换器的开关频率，并尽可能地减少后置稳压器滤波。内部软启动时间和电流限制保护可减小启动期间的浪涌电流，从而尽可能降低输入电容。还包括标准保护特性，例如过流和过热保护。 封装信息 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981A 封装信息 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981A 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB 器件型号 封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE 封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB 器件型号封装#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE #GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/DEVINFONOTE封装尺寸#GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB #GUID-E0F2B2F0-0166-4176-9938-82761AC9EFA5/LI_T3R_KTT_PZB LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981A LP2981 SOT-23 (5) 2.90mm x 2.80mm LP2981SOT-23 (5)2.90mm x 2.80mm LP2981A LP2981A 有关详细信息，请参阅 。 封装尺寸（长 x 宽）为标称值，并包括引脚（如适用）。 有关详细信息，请参阅 。封装尺寸（长 x 宽）为标称值，并包括引脚（如适用）。 典型应用电路 压降电压与温度间的关系（新芯片） 典型应用电路 压降电压与温度间的关系（新芯片） 典型应用电路 典型应用电路 压降电压与温度间的关系（新芯片） 压降电压与温度间的关系（新芯片） Table of Contents yes Table of Contents yes yes yes Pin Configuration and Functions DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. Pin Configuration and Functions DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. DBV Package, 5-Pin SOT-23 (Top View) DBV Package, 5-Pin SOT-23 (Top View) DBV Package,5-Pin SOT-23(Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. PIN TYPE DESCRIPTION NO. NAME PIN TYPE DESCRIPTION PINTYPEDESCRIPTION NO. NAME NO.NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 1INIInput supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. 2 GND — Common ground (device substrate). 2GND—Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 3ON/OFF OFFIEnable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused.OFFIN 4 NC — Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 4NC—Not internally connected. This pin can be left open or tied to ground for improved thermal performance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information. 5OUTOOutput of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See for more information.#GUID-ED9A8727-F3EA-4F22-AF2B-3231FB59812A/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22 The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Machine model (MM) ±100 N/A JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. Thermal Information THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Electrical Characteristics specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 1000 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Typical Characteristics Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 10 µF, CIN = 1 µF all voltage options, ON/ OFF pin tied to VIN. Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs VIN (New Chip) VOUT = 3.3 V Output Voltage vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Dropout Voltage (VDO) vs Temperature (New Chip) Dropout Voltage (VDO) vs Load Current (New Chip) Ground Pin Current (IGND) vs Temperature (New Chip) Ground Pin Current (IGND) vs Load Current (New Chip) Input Current vs Input Voltage (VIN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current vs Time (New Chip) VIN = 6.0 V Short Circuit Current vs Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current vs Temperature (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip) Ripple Rejection vs Load Current (IL) and Frequency (New Chip) Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip) Output Noise Density vs Load Current (IL) Frequency (New Chip) Output Noise Density vs Output Capacitor (CL) Frequency (New Chip) Output Reverse Leakage vs Temperature (New Chip) Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 4.3 V ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 16.0 V ON/ OFF Threshold vs Temperature (New Chip) Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 MIN MAX UNIT MIN MAX UNIT MINMAXUNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 VIN Continuous input voltage range (for legacy chip) –0.3 16 V VIN IN Continuous input voltage range (for legacy chip)–0.316V Continuous input voltage range (for new chip) –0.3 18 Continuous input voltage range (for new chip) –0.318 VOUT Output voltage range (for legacy chip) –0.3 9 VOUT OUTOutput voltage range (for legacy chip)–0.39 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) Output voltage range (for new chip) –0.3VIN + 0.3 or 9 (whichever is smaller)IN VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 VON/OFF ON/OFF OFFON/OFF pin voltage range (for legacy chip)OFF–0.316 ON/OFF pin voltage range (for new chip) –0.3 18 ON/OFF pin voltage range (for new chip)OFF–0.318 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 VIN – VOUT INOUTInput-output voltage (for legacy chip)–0.316 Input-output voltage (for new chip) –0.3 18 Input-output voltage (for new chip)–0.318 Current Maximum output current Internally limited mA CurrentMaximum output currentInternally limitedmA Temperature Operating junction, TJ –55 150 °C TemperatureOperating junction, TJ J–55150°C Storage, Tstg –65 150 Storage, Tstg stg–65150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.Absolute Maximum RatingsAbsolute Maximum RatingsRecommended Operating ConditionsRecommended Operating ConditionsAbsolute Maximum RatingsAll voltages with respect to GND. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Machine model (MM) ±100 N/A JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Machine model (MM) ±100 N/A JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Machine model (MM) ±100 N/A VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Machine model (MM) ±100 N/A VALUE (Legacy Chip) VALUE (New Chip) UNIT VALUE (Legacy Chip) VALUE (New Chip) UNIT VALUE (Legacy Chip)VALUE (New Chip)UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Machine model (MM) ±100 N/A V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 ±2000 ±3000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/HBM_COMM_SF2±2000±3000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 ±500 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377653/CDM_COMM_SF2±500±1000 Machine model (MM) ±100 N/A Machine model (MM)±100N/A JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C VIN Supply input voltage (for legacy chip) 2.2 16 V VIN INSupply input voltage (for legacy chip)2.216V Supply input voltage (for new chip) 2.5 16 Supply input voltage (for new chip)2.516 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 VIN – VOUT INOUTInput-output differential (for legacy chip)0.711 Input-output differential (for new chip) 0 16 Input-output differential (for new chip)016 VOUT Output voltage (for new chip) 1.2 5 VOUT OUTOutput voltage (for new chip)1.25 VON/OFF Enable voltage (for legacy chip) 0 VIN VON/OFF ON/OFF OFFEnable voltage (for legacy chip)0VIN IN Enable voltage (for new chip) 0 16 Enable voltage (for new chip)016 IOUT Output current 0 100 mA IOUT OUTOutput current0100mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 Input capacitor 1 µF CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 IN#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1Input capacitor1µF COUT Output capacitor (for legacy chip)  2.2 4.7 COUT OUTOutput capacitor (for legacy chip) 2.24.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 1 2.2 200 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378362/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF112.2200 TJ Operating junction temperature –40 125 °C TJ JOperating junction temperature–40125°C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. Thermal Information THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Thermal Information THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 UNIT THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/APPNOTE_LP2985_SF1Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377647/THERMALFOOTER_SF1_SF1UNIT DBV (SOT23-5) DBV (SOT23-5) DBV (SOT23-5)DBV (SOT23-5) 5 PINS 5 PINS 5 PINS5 PINS RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W RθJA Junction-to-ambient thermal resistance 205.2 178.6 °C/W RθJA θJAJunction-to-ambient thermal resistance205.2178.6°C/W RθJC(top) Junction-to-case (top) thermal resistance 11.83 77.9 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance11.8377.9°C/W RθJB Junction-to-board thermal resistance 37.7 47.2 °C/W RθJB θJBJunction-to-board thermal resistance37.747.2°C/W ψJT Junction-to-top characterization parameter 12.2 15.9 °C/W ψJT JTJunction-to-top characterization parameter12.215.9°C/W ψJB Junction-to-board characterization parameter 33.8 46.9 °C/W ψJB JBJunction-to-board characterization parameter33.846.9°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal MetricsThermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Impact of board layout on LDO thermal performance Impact of board layout on LDO thermal performance Electrical Characteristics specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 1000 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Electrical Characteristics specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 1000 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 1000 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)JINOUT(nom)OUTON/OFFINOUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 1000 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 1000 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % ∆VOUT OUTOutput voltage toleranceIL = 1 mALLegacy chip (Standard grade)–1.251.25% Legacy chip (A grade) –0.75 0.75 % Legacy chip (A grade)–0.750.75% New chip –0.5 0.5 % New chip–0.50.5% 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % 1 mA < IL < 100 mALLegacy chip (Standard grade)–2.02.0% Legacy chip (A grade) –1.0 1.0 % Legacy chip (A grade)–1.01.0% New chip –0.5 0.5 % New chip–0.50.5% 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°CLJ Legacy chip (Standard grade)–3.53.5% Legacy chip (A grade) –2.5 2.5 % Legacy chip (A grade)–2.52.5% New chip –1 1 % New chip–11% ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V ΔVOUT(ΔVIN) OUT(ΔVIN)Line regulationVO(NOM) + 1 V ≤ VIN ≤ 16 VO(NOM)INLegacy chip0.0070.014%/V New chip 0.002 0.014 New chip0.0020.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CO(NOM)INJLegacy chip0.0070.032 New chip 0.002 0.032 New chip0.0020.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A ΔVOUT(ΔILOAD) OUT(ΔILOAD)Load regulation1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 VLJ INO(NOM)New chip0.10.5%/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 IOUT = 0 mA Legacy chip 1 3 mV VIN - VOUT INOUTDropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378396/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1_SF1IOUT = 0 mAOUTLegacy chip13mV New chip 1 2.75 New chip12.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip5 New chip 3 New chip3 IOUT = 1 mA Legacy chip 7 10 IOUT = 1 mAOUTLegacy chip710 New chip 11.5 14 New chip11.514 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip15 New chip 17 New chip17 IOUT = 25 mA Legacy chip 70 100 IOUT = 25 mAOUTLegacy chip70100 New chip 110 132 New chip110132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip150 New chip 167 New chip167 IOUT = 100 mA Legacy chip 200 250 IOUT = 100 mAOUTLegacy chip200250 New chip 160 175 New chip160175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip375 New chip 218 New chip218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA IGND GND GND pin currentIOUT = 0 mAOUTLegacy chip6595µA New chip 69 95 New chip6995 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip125 New chip 123 New chip123 IOUT = 1 mA Legacy chip 80 110 IOUT = 1 mAOUTLegacy chip80110 New chip 78 110 New chip78110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip170 New chip 140 New chip140 IOUT = 25 mA Legacy chip 200 300 IOUT = 25 mAOUTLegacy chip200300 New chip 225 295 New chip225295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip550 New chip 345 New chip345 IOUT = 100 mA Legacy chip 600 1000 IOUT = 100 mAOUTLegacy chip6001000 New chip 620 790 New chip620790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1700 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip1700 New chip 950 New chip950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 VON/OFF < 0.3 V, VIN = 16 VON/OFFINLegacy chip0.010.8 New chip 1.25 1.75 New chip1.251.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 105°CON/OFFINJ Legacy chip0.052 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C 5 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°CON/OFFINJ 5 New chip 1.12 2.75 New chip1.122.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO+ UVLO+Rising bias supply UVLOVIN rising, –40°C ≤ TJ ≤ 125°CINJ New chip2.22.4V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO- UVLO-Falling bias supply UVLOVIN falling, –40°C ≤ TJ ≤ 125°CINJ 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 VUVLO(HYST) UVLO(HYST)UVLO hysteresis–40°C ≤ TJ ≤ 125°CJ 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA IO(SC) O(SC)Short Output CurrentRL = 0 Ω (steady state)LLegacy chip150mA New chip 150 New chip150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V VON/OFF ON/OFF OFFON/OFF input voltageOFFLow = Output OFFLegacy chip0.5V New chip 0.72 New chip0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°COUTINJ Legacy chip0.15 New chip 0.15 New chip0.15 High = Output ON Legacy chip 1.4 High = Output ONLegacy chip1.4 New chip 0.85 New chip0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°COUTINJ Legacy chip1.6 New chip 1.6 New chip1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA ION/OFF ON/OFF OFFON/OFF input currentVON/OFF = 0 VON/OFFLegacy chip0.01µA New chip 0.42 New chip0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CON/OFFOUTINJ Legacy chip–1 New chip –0.9 New chip–0.9 VON/OFF = 5 V Legacy chip 5 VON/OFF = 5 VON/OFFLegacy chip5 New chip 0.011 New chip0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CON/OFFOUTINJ Legacy chip15 New chip 2.20 New chip2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 400 mA IO(PK) O(PK)Peak output currentVOUT ≥ VO(NOM) –5% (steady state)OUTO(NOM)Legacy chip400mA New chip 350 New chip350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB ΔVO/ΔVIN OINRipple Rejectionf = 1 kHz, COUT = 10 µFOUTLegacy chip63dB New chip 75 New chip75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Vn nOutput noise voltageBandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mAOUT OUTLOADLegacy chip160µVRMS VRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mAOUT OUTLOADNew chip140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd+ sd+Thermal shutdown thresholdShutdown, temperature increasingNew chip170°C Tsd- Reset, temperature decreasing 150 Tsd- sd-Reset, temperature decreasing150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.DODOINOUT(nom) Typical Characteristics Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 10 µF, CIN = 1 µF all voltage options, ON/ OFF pin tied to VIN. Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs VIN (New Chip) VOUT = 3.3 V Output Voltage vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Dropout Voltage (VDO) vs Temperature (New Chip) Dropout Voltage (VDO) vs Load Current (New Chip) Ground Pin Current (IGND) vs Temperature (New Chip) Ground Pin Current (IGND) vs Load Current (New Chip) Input Current vs Input Voltage (VIN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current vs Time (New Chip) VIN = 6.0 V Short Circuit Current vs Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current vs Temperature (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip) Ripple Rejection vs Load Current (IL) and Frequency (New Chip) Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip) Output Noise Density vs Load Current (IL) Frequency (New Chip) Output Noise Density vs Output Capacitor (CL) Frequency (New Chip) Output Reverse Leakage vs Temperature (New Chip) Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 4.3 V ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 16.0 V ON/ OFF Threshold vs Temperature (New Chip) Typical Characteristics Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 10 µF, CIN = 1 µF all voltage options, ON/ OFF pin tied to VIN. Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs VIN (New Chip) VOUT = 3.3 V Output Voltage vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Dropout Voltage (VDO) vs Temperature (New Chip) Dropout Voltage (VDO) vs Load Current (New Chip) Ground Pin Current (IGND) vs Temperature (New Chip) Ground Pin Current (IGND) vs Load Current (New Chip) Input Current vs Input Voltage (VIN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current vs Time (New Chip) VIN = 6.0 V Short Circuit Current vs Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current vs Temperature (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip) Ripple Rejection vs Load Current (IL) and Frequency (New Chip) Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip) Output Noise Density vs Load Current (IL) Frequency (New Chip) Output Noise Density vs Output Capacitor (CL) Frequency (New Chip) Output Reverse Leakage vs Temperature (New Chip) Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 4.3 V ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 16.0 V ON/ OFF Threshold vs Temperature (New Chip) Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 10 µF, CIN = 1 µF all voltage options, ON/ OFF pin tied to VIN. Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs VIN (New Chip) VOUT = 3.3 V Output Voltage vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Dropout Voltage (VDO) vs Temperature (New Chip) Dropout Voltage (VDO) vs Load Current (New Chip) Ground Pin Current (IGND) vs Temperature (New Chip) Ground Pin Current (IGND) vs Load Current (New Chip) Input Current vs Input Voltage (VIN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current vs Time (New Chip) VIN = 6.0 V Short Circuit Current vs Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current vs Temperature (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip) Ripple Rejection vs Load Current (IL) and Frequency (New Chip) Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip) Output Noise Density vs Load Current (IL) Frequency (New Chip) Output Noise Density vs Output Capacitor (CL) Frequency (New Chip) Output Reverse Leakage vs Temperature (New Chip) Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 4.3 V ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 16.0 V ON/ OFF Threshold vs Temperature (New Chip) Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 10 µF, CIN = 1 µF all voltage options, ON/ OFF pin tied to VIN.AINO(NOM)OUTINOFFIN Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs VIN (New Chip) VOUT = 3.3 V Output Voltage vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Dropout Voltage (VDO) vs Temperature (New Chip) Dropout Voltage (VDO) vs Load Current (New Chip) Ground Pin Current (IGND) vs Temperature (New Chip) Ground Pin Current (IGND) vs Load Current (New Chip) Input Current vs Input Voltage (VIN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current vs Time (New Chip) VIN = 6.0 V Short Circuit Current vs Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current vs Temperature (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip) Ripple Rejection vs Load Current (IL) and Frequency (New Chip) Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip) Output Noise Density vs Load Current (IL) Frequency (New Chip) Output Noise Density vs Output Capacitor (CL) Frequency (New Chip) Output Reverse Leakage vs Temperature (New Chip) Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 4.3 V ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 16.0 V ON/ OFF Threshold vs Temperature (New Chip) Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 VINOUT Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Load Current (New Chip) VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 VINOUT Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Load Regulation vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 VINOUT Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage vs Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 VINOUT Output Voltage vs VIN (New Chip) VOUT = 3.3 V Output Voltage vs VIN (New Chip)IN VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 VOUT Output Voltage vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Output Voltage vs VIN and Temperature (New Chip)IN VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Line Regulation vs VIN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation vs VIN and Temperature (New Chip)IN VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Dropout Voltage (VDO) vs Temperature (New Chip) Dropout Voltage (VDO) vs Temperature (New Chip)DO Dropout Voltage (VDO) vs Load Current (New Chip) Dropout Voltage (VDO) vs Load Current (New Chip)DO Ground Pin Current (IGND) vs Temperature (New Chip) Ground Pin Current (IGND) vs Temperature (New Chip)GND Ground Pin Current (IGND) vs Load Current (New Chip) Ground Pin Current (IGND) vs Load Current (New Chip)GND Input Current vs Input Voltage (VIN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Input Current vs Input Voltage (VIN) (New Chip)IN VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mAOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μFOUTOUT Short Circuit Current vs Time (New Chip) VIN = 6.0 V Short Circuit Current vs Time (New Chip) VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 VIN Short Circuit Current vs Time (New Chip) VIN = 16.0 V Short Circuit Current vs Time (New Chip) VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 VIN Instantaneous Short Circuit Current vs Temperature (New Chip) Instantaneous Short Circuit Current vs Temperature (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip) Short Circuit Current vs Output Voltage (VOUT) (New Chip)OUT Ripple Rejection vs Load Current (IL) and Frequency (New Chip) Ripple Rejection vs Load Current (IL) and Frequency (New Chip)L Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip) Ripple Rejection vs Output Capacitor (CL) and Frequency (New Chip)L Output Noise Density vs Load Current (IL) Frequency (New Chip) Output Noise Density vs Load Current (IL) Frequency (New Chip)L Output Noise Density vs Output Capacitor (CL) Frequency (New Chip) Output Noise Density vs Output Capacitor (CL) Frequency (New Chip)L Output Reverse Leakage vs Temperature (New Chip) Output Reverse Leakage vs Temperature (New Chip) Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩOUTL Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 4.3 V ON/ OFF Pin Current vs VON/ OFF (New Chip)OFFON/ OFF OFF VIN = 4.3 V VIN = 4.3 V VIN = 4.3 V VIN = 4.3 V VIN = 4.3 V VIN = 4.3 VIN ON/ OFF Pin Current vs VON/ OFF (New Chip) VIN = 16.0 V ON/ OFF Pin Current vs VON/ OFF (New Chip)OFFON/ OFF OFF VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 VIN ON/ OFF Threshold vs Temperature (New Chip) ON/ OFF Threshold vs Temperature (New Chip)OFF Detailed Description Overview The LP2981 and LP2981A are fixed-output, high PSRR, low-dropout regulators that offer exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. Functional Block Diagram Feature Description Output Enable F Added Output Enable section no The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. Dropout Voltage F Added Dropout Voltage section no Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Current Limit F Added Current Limit section no The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Thermal Shutdown F Added Thermal Shutdown section no The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Thermal shutdown circuit specifications are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Output Pulldown F Added Output Pulldown section no The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Device Functional Modes Device Functional Mode Comparison #GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Detailed Description Overview The LP2981 and LP2981A are fixed-output, high PSRR, low-dropout regulators that offer exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. Overview The LP2981 and LP2981A are fixed-output, high PSRR, low-dropout regulators that offer exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. The LP2981 and LP2981A are fixed-output, high PSRR, low-dropout regulators that offer exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. The LP2981 and LP2981A are fixed-output, high PSRR, low-dropout regulators that offer exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current.This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. Functional Block Diagram Functional Block Diagram Feature Description Output Enable F Added Output Enable section no The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. Dropout Voltage F Added Dropout Voltage section no Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Current Limit F Added Current Limit section no The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Thermal Shutdown F Added Thermal Shutdown section no The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Thermal shutdown circuit specifications are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Output Pulldown F Added Output Pulldown section no The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Feature Description Output Enable F Added Output Enable section no The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. Output Enable F Added Output Enable section no F Added Output Enable section no F Added Output Enable section no FAdded Output Enable sectionOutput Enableno The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device.OFFOFFOFFOFFOFFOFFFor the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage.OFFOFF Dropout Voltage F Added Dropout Voltage section no Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Dropout Voltage F Added Dropout Voltage section no F Added Dropout Voltage section no F Added Dropout Voltage section no FAdded Dropout Voltage sectionDropout Voltageno Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well.DOINOUTRATEDRATEDOUTFor a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. DS(ON)DS(ON) R D S ( O N ) =   V D O I R A T E D R D S ( O N ) =   V D O I R A T E D R D S ( O N ) =   V D O I R A T E D R D S ( O N ) R R D S ( O N ) DS(ON)=  V D O I R A T E D V D O V D O V V D O DO I R A T E D I R A T E D I I R A T E D RATED Current Limit F Added Current Limit section no The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Current Limit F Added Current Limit section no F Added Current Limit section no F Added Current Limit section no FAdded Current Limit sectionCurrent Limitno The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table.CLCLThe output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note.INOUTCL Know Your Limits Know Your Limits shows a diagram of the current limit. Current Limit Current Limit Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no F Added Undervoltage Lockout (UVLO) section no F Added Undervoltage Lockout (UVLO) section no FAdded Undervoltage Lockout (UVLO) sectionUndervoltage Lockout (UVLO)no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Thermal Shutdown F Added Thermal Shutdown section no The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Thermal shutdown circuit specifications are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Thermal Shutdown F Added Thermal Shutdown section no F Added Thermal Shutdown section no F Added Thermal Shutdown section no FAdded Thermal Shutdown sectionThermal Shutdownno The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Thermal shutdown circuit specifications are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Thermal shutdown circuit specifications are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Thermal shutdown circuit specifications are defined in .JSD(shutdown)SD(reset)The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes.INOUTFor reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Output Pulldown F Added Output Pulldown section no The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Output Pulldown F Added Output Pulldown section no F Added Output Pulldown section no F Added Output Pulldown section no FAdded Output Pulldown sectionOutput Pulldownno The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO When the device is disabled (VON/OFF < VON/OFF(LOW))ON/OFF OFFON/OFF(LOW)OFFIf 1.0 V < VIN < VUVLO INUVLODo not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Device Functional Modes Device Functional Mode Comparison #GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Device Functional Modes Device Functional Mode Comparison #GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Device Functional Mode Comparison #GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) #GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) #GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values.#GUID-C934E2DD-9E4E-4F7E-87D4-CB1EE993DC55/X3048 Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ OPERATING MODE PARAMETER OPERATING MODEPARAMETER VIN VON/OFF IOUT TJ VIN INVON/OFF ON/OFF OFFIOUT OUTTJ J Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Normal operationVIN > VOUT(nom) + VDO and VIN > VIN(min) INOUT(nom)DOININ(min)VON/OFF > VON/OFF(HI) ON/OFF OFFON/OFF(HI)OFFIOUT < IOUT(max) OUTOUT(max)TJ < TSD(shutdown) JSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operationVIN(min) < VIN < VOUT(nom) + VDO IN(min)INOUT(nom)DOVON/OFF > VON/OFF(HI) ON/OFF OFFON/OFF(HI)OFFIOUT < IOUT(max) OUTOUT(max)TJ < TSD(shutdown) JSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device)VIN < VUVLO INUVLOVON/OFF < VON/OFF(LOW) ON/OFF OFFON/OFF(LOW)OFFNot applicableTJ > TSD(shutdown) JSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)OUT(nom)DOThe output current is less than the current limit (IOUT < ICL)OUTCLThe device junction temperature is less than the thermal shutdown temperature (TJ < TSD)JSDThe ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling thresholdOFFOFF Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations.When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region.INOUT(NOM)DOnotOUT(NOM)DO Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.OFFOFF Application and Implementation 以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 Application Information The LP2981 and LP2981A are linear voltage regulators operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to provide a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. Recommended Capacitor Types F Added Recommended Capacitor Types section no Recommended Capacitors for the Legacy Chip Tantalum Capacitors For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. Aluminum Capacitors For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no Input Capacitor For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output Capacitor For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Estimating Junction Temperature F Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the top-center of the device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use these metrics, see the Semiconductor and IC Package Thermal Metrics application note. Power Dissipation (PD) F Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Reverse Current F Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Typical Application LP2981 Typical Application Minimum COUT value for stability (can be increased without limit for improved stability and transient response). ON/ OFF must be actively terminated. Connect to VIN if shutdown feature is not used. For the new chip, Pin 4 (NC) is not internally connected. Design Requirements #GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 lists the parameters for this application. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin. Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Application and Implementation 以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。 Application Information The LP2981 and LP2981A are linear voltage regulators operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to provide a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. Recommended Capacitor Types F Added Recommended Capacitor Types section no Recommended Capacitors for the Legacy Chip Tantalum Capacitors For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. Aluminum Capacitors For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no Input Capacitor For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output Capacitor For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Estimating Junction Temperature F Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the top-center of the device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use these metrics, see the Semiconductor and IC Package Thermal Metrics application note. Power Dissipation (PD) F Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Reverse Current F Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Application Information The LP2981 and LP2981A are linear voltage regulators operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to provide a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. The LP2981 and LP2981A are linear voltage regulators operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to provide a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. The LP2981 and LP2981A are linear voltage regulators operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current.Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to provide a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. Recommended Capacitor Types F Added Recommended Capacitor Types section no Recommended Capacitors for the Legacy Chip Tantalum Capacitors For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. Aluminum Capacitors For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. Recommended Capacitor Types F Added Recommended Capacitor Types section no F Added Recommended Capacitor Types section no F Added Recommended Capacitor Types section no FAdded Recommended Capacitor Types sectionRecommended Capacitor Typesno Recommended Capacitors for the Legacy Chip Tantalum Capacitors For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. Aluminum Capacitors For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the Legacy Chip Tantalum Capacitors For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Tantalum Capacitors For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer data sheet to verify that the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. Ceramic Capacitors For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This recommendation is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A measured 2.2-μF ceramic capacitor is verified to have an ESR of approximately 15 mΩ, which is low enough to cause oscillations. If a ceramic capacitor is used on the output, a 1-Ω resistor is required to be placed in series with the capacitor. Aluminum Capacitors For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Aluminum Capacitors For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of the steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value. The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance.Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the Recommended Operating Conditions table account for an effective capacitance of approximately 50% of the nominal value.Recommended Operating Conditions Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no Input Capacitor For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output Capacitor For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no F Added Input and Output Capacitor Requirements section no F Added Input and Output Capacitor Requirements section no FAdded Input and Output Capacitor Requirements sectionInput and Output Capacitor Requirementsno Input Capacitor For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Input Capacitor For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. INFor the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output Capacitor For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Output Capacitor For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ).For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Estimating Junction Temperature F Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the top-center of the device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use these metrics, see the Semiconductor and IC Package Thermal Metrics application note. Estimating Junction Temperature F Added Estimating Junction Temperature section no F Added Estimating Junction Temperature section no F Added Estimating Junction Temperature section no FAdded Estimating Junction Temperature sectionEstimating Junction Temperatureno The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the top-center of the device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use these metrics, see the Semiconductor and IC Package Thermal Metrics application note. The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the top-center of the device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use these metrics, see the Semiconductor and IC Package Thermal Metrics application note. The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the top-center of the device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature.JTJBJJTTJBBTJ = TT + ψJT × PD JTJTDwhere: PD is the dissipated power TT is the temperature at the center-top of the device package PD is the dissipated powerDTT is the temperature at the center-top of the device packageTTJ = TB + ψJB × PD JBJBDwhere: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edgeBFor detailed information on the thermal metrics and how to use these metrics, see the Semiconductor and IC Package Thermal Metrics application note. Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal Metrics Power Dissipation (PD) F Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Power Dissipation (PD)D F Added Power Dissipation (PD) section no F Added Power Dissipation (PD) section no F Added Power Dissipation (PD) section no FAdded Power Dissipation (PD) sectionPower Dissipation (PD)Dno Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress.To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD).DPD = (VIN – VOUT) × IOUT DINOUTOUTPower dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation.For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation.The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA).AθJAA TJ = TA + (RθJA × PD) JAθJADThermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization.θJA An empirical analysis of the impact of board layout on LDO thermal performance An empirical analysis of the impact of board layout on LDO thermal performanceθJAThermal Information Reverse Current F Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Reverse Current F Added Reverse Current section no F Added Reverse Current section no F Added Reverse Current section no FAdded Reverse Current sectionReverse Currentno Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device.Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V.OUTIN If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If the device has a large COUT and the input supply collapses with little or no load currentOUTThe output is biased when the input supply is not establishedThe output is biased above the input supplyIf reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Example Circuit for Reverse Current Protection Using a Schottky Diode Typical Application LP2981 Typical Application Minimum COUT value for stability (can be increased without limit for improved stability and transient response). ON/ OFF must be actively terminated. Connect to VIN if shutdown feature is not used. For the new chip, Pin 4 (NC) is not internally connected. Design Requirements #GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 lists the parameters for this application. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin. Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Typical Application LP2981 Typical Application Minimum COUT value for stability (can be increased without limit for improved stability and transient response). ON/ OFF must be actively terminated. Connect to VIN if shutdown feature is not used. For the new chip, Pin 4 (NC) is not internally connected. LP2981 Typical Application Minimum COUT value for stability (can be increased without limit for improved stability and transient response). ON/ OFF must be actively terminated. Connect to VIN if shutdown feature is not used. For the new chip, Pin 4 (NC) is not internally connected. LP2981 Typical Application Minimum COUT value for stability (can be increased without limit for improved stability and transient response). ON/ OFF must be actively terminated. Connect to VIN if shutdown feature is not used. For the new chip, Pin 4 (NC) is not internally connected. LP2981 Typical ApplicationMinimum COUT value for stability (can be increased without limit for improved stability and transient response).OUTON/ OFF must be actively terminated. Connect to VIN if shutdown feature is not used.OFFINFor the new chip, Pin 4 (NC) is not internally connected. Design Requirements #GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 lists the parameters for this application. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Design Requirements #GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 lists the parameters for this application. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB #GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 lists the parameters for this application. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB #GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 lists the parameters for this application.#GUID-1DDB0F44-A12A-43C5-9FC4-A010AA39E58A/T776633-11 Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB PARAMETER DESIGN REQUIREMENT PARAMETER DESIGN REQUIREMENT PARAMETERDESIGN REQUIREMENT Input voltage 12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Input voltage 12 V ±10%, provided by an external regulator Input voltage12 V ±10%, provided by an external regulator Output voltage 3.3 V ±1% Output voltage3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) Output current100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS RMS noise, 300 Hz to 50 kHz< 1 mVRMS RMS PSRR at 1 kHz > 40 dB PSRR at 1 kHz> 40 dB Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin. Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin. ON and OFF Input OperationOFF K Changed layout of National Data Sheet to TI format yes K Changed layout of National Data Sheet to TI format yes K Changed layout of National Data Sheet to TI format yes KChanged layout of National Data Sheet to TI formatyes The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin. The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin. The LP2981/A is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating).OFFINOFFnotFor proper operation, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turn-on or turn-off voltage thresholds which specify an ON or OFF state (see ).OFFOFFThe ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981 and LP2891A input voltage or another logic supply. The high-level voltage can exceed the LP2981 and LP2891A input voltage, but must remain within the ratings list in for the ON/ OFF pin.OFFOFF Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μFOUTOUT 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μFOUTL 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μFOUTOUT 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μFOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mAOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μFOUTOUT Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩOUTL Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL Power Supply Recommendations The LP2981 is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. Power Supply Recommendations The LP2981 is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. The LP2981 is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. The LP2981 is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. The LP2981 is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. Layout Layout Guidelines For best overall performance, place all circuit components on the same side of the printed-circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. Layout Example Recommended Layout Layout Layout Guidelines For best overall performance, place all circuit components on the same side of the printed-circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. Layout Guidelines For best overall performance, place all circuit components on the same side of the printed-circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. For best overall performance, place all circuit components on the same side of the printed-circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. For best overall performance, place all circuit components on the same side of the printed-circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. Layout Example Recommended Layout Layout Example Recommended Layout Recommended Layout Recommended Layout Recommended Layout Device and Documentation Support Device Nomenclature H Added Device Nomenclature section yes Available Options PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Documentation Support Related Documentation H Added three references to Related Documentation yes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 支持资源 TI E2E 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索现有解答或提出自己的问题，获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的使用条款。 Trademarks 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 Device and Documentation Support Device Nomenclature H Added Device Nomenclature section yes Available Options PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Device Nomenclature H Added Device Nomenclature section yes H Added Device Nomenclature section yes H Added Device Nomenclature section yes HAdded Device Nomenclature sectionDevice Nomenclatureyes Available Options PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Available Options PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Available Options PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. Available Options PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 VOUT PRODUCT#GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161 #GUID-84D0D562-4187-45B7-A349-BA3E92AAD93A/NSBVS047_111620041119161VOUT OUT LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. LP2981c-xxyyyz Legacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2981c-xxyyyz Legacy chip cxxyyyzLegacy chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel.cxxyyyz LP2981c-xxyyyzM3 New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. LP2981c-xxyyyzM3 New chip cxxyyyzM3 M3New chip c is for the accuracy of LDO output. xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology.cxxyyyzM3 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com.www.ti.com Documentation Support Related Documentation H Added three references to Related Documentation yes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Documentation Support Related Documentation H Added three references to Related Documentation yes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Related Documentation H Added three references to Related Documentation yes H Added three references to Related Documentation yes H Added three references to Related Documentation yes HAdded three references to Related Documentation Related Documentationyes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Texas Instruments, LDO Noise Demystified , application note LDO Noise Demystified LDO Noise DemystifiedTexas Instruments, LDO PSRR Measurement Simplified , application note LDO PSRR Measurement Simplified LDO PSRR Measurement SimplifiedTexas Instruments, A Topical Index of TI LDO Application Notes , application note A Topical Index of TI LDO Application Notes A Topical Index of TI LDO Application Notes Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.Alert me 支持资源 TI E2E 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索现有解答或提出自己的问题，获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的使用条款。 支持资源 TI E2E 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索现有解答或提出自己的问题，获得所需的快速设计帮助。 链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的使用条款。 TI E2E 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索现有解答或提出自己的问题，获得所需的快速设计帮助。 TI E2E 中文支持论坛TI E2E链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI 的使用条款。使用条款 Trademarks Trademarks 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 静电放电警告 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理和安装程序，可能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 术语表 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。 TI 术语表 TI 术语表本术语表列出并解释了术语、首字母缩略词和定义。 Revision History yes July 2016 December 2023 G H Revision History yes July 2016 December 2023 G H yes July 2016 December 2023 G H yesJuly 2016December 2023GH Revision History yes August 2008 July 2016 F G Revision History yes August 2008 July 2016 F G yes August 2008 July 2016 F G yesAugust 2008July 2016FG Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. 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For browser-based versions of this data sheet, refer to the left-hand navigation. 重要声明和免责声明 TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。 TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 重要声明和免责声明 TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。 TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。 TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。 TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。 TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。 TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。TI 的销售条款ti.com TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE IMPORTANT NOTICE 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023，德州仪器 (TI) 公司 Copyright © 2023，德州仪器 (TI) 公司 table for stability.