ZHCSSD8F april   2000  – july 2023 LP2980-ADJ

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
        1. 8.1.2.1 Recommended Capacitors for the New Chip
        2. 8.1.2.2 Recommended Capacitors for the Legacy Chip
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Feed-Forward Capacitor (CFF)
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting VOUT For the LP2980-ADJ LDO
        2. 8.2.2.2 ON/OFF Input Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Supply input voltage (for legacy chip) 2.2 16 V
Supply input voltage (for new chip) 2.5 16
VOUT Output voltage (for legacy chip) 1.225 15.0
Output voltage (for new chip) 1.2 15.0
VADJ ADJ voltage (for legacy chip) 1.225
ADJ voltage (for new chip) 1.2
VON/OFF Enable voltage (for legacy chip) 0 VIN
Enable voltage (for new chip) 0 16
IOUT Output current 0 50 mA
CIN(3) Input capacitor 1 μF
COUT Output capacitor (for legacy chip) (2) 2.2 4.7
Output capacitance (for new chip) (1) 1 2.2 200
CFF (4) Feed-forward capacitor (for legacy chip) 7 pF
Feed-forward capacitor (for new chip) 10
TJ Operating junction temperature –40 125 °C
(1) For new chip, all capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability.
(2) For legacy chip, minimum output capacitance of 2.2 μF is required with ESR range suggested in the Recommended Capacitor Types section
(3) For legacy chip, an input capacitor of value ≥1 μF is required. It must be located not more than 0.5″ from the input pin and returned to a clean analog ground.
(4) Regarding the requirement of feed-forward capacitor (CFF), see the Feed-Forward Capacitor section.