ZHCSSD8F april   2000  – july 2023 LP2980-ADJ

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
        1. 8.1.2.1 Recommended Capacitors for the New Chip
        2. 8.1.2.2 Recommended Capacitors for the Legacy Chip
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Feed-Forward Capacitor (CFF)
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting VOUT For the LP2980-ADJ LDO
        2. 8.2.2.2 ON/OFF Input Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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8.1.4 Feed-Forward Capacitor (CFF)

A feed-forward capacitor (CFF) can be connected from the VOUT pin to the ADJ pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.

CFF and R1 form a zero in the loop gain at frequency fZ, whereas CFF, R1, and R2 form a pole in the loop gain at frequency fP. CFF zero and pole frequencies can be calculated from the following equations:

Equation 4. fZ = 1 / (2 × π × CFF × R1)
Equation 5. fP = 1 / (2 × π × CFF × (R1 || R2))

For the legacy chip, a feed-forward capacitor (CFF) of 7 pF is required, because this capacitor provides the lead compensation necessary for loop stability. Use a temperature-stable ceramic capacitor (NPO or COG type).

For the new chip, a CFF ≥ 10 pF is required for stability only if the feedback divider current is less than 5 μA. The following equation calculates the feedback divider current.

Equation 6. IFB_Divider = VOUT / (R1 + R2)

To avoid start-up time increases from CFF, limit the product CFF × R1 < 50 µs.

For an output voltage of 1.2 V with the ADJ pin tied to the VOUT pin, no CFF is used.