ZHCSSD8F april   2000  – july 2023 LP2980-ADJ

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage
      3. 7.3.3 Current Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Output Pulldown
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Feedback Resistors
      2. 8.1.2 Recommended Capacitor Types
        1. 8.1.2.1 Recommended Capacitors for the New Chip
        2. 8.1.2.2 Recommended Capacitors for the Legacy Chip
      3. 8.1.3 Input and Output Capacitor Requirements
      4. 8.1.4 Feed-Forward Capacitor (CFF)
      5. 8.1.5 Reverse Current
      6. 8.1.6 Power Dissipation (PD)
      7. 8.1.7 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting VOUT For the LP2980-ADJ LDO
        2. 8.2.2.2 ON/OFF Input Operation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6.5 Electrical Characteristics

specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Reference Voltage Legacy Chip IL = 1mA 1.213 1.225 1.237 V
New Chip 1.194 1.2 1.206
Legacy Chip 1 mA < IL < 50 mA, VOUT + 1 ≤ VIN ≤ 16V, TJ = 25°C 1.206 1.225 1.243
New Chip 1.1928 1.2 1.206
Legacy Chip 1 mA < IL < 50 mA, VOUT + 1 ≤ VIN ≤ 16V, –40°C ≤ TJ ≤ 125°C 1.182 1.225 1.268
New Chip 1.1892 1.2 1.2108
ΔVREF/ΔVIN Reference Voltage Line Regulation Legacy Chip 2.5V ≤ VIN ≤ 16V, TJ = 25°C 3.0 6.0 mV
New Chip –0.5 4.0
Legacy Chip 2.5V ≤ VIN ≤ 16V, –40°C ≤ TJ ≤ 125°C 15.0
New Chip 4.25
VIN - VOUT Dropout voltage Legacy Chip IL = 0mA 1 3 mV
New Chip 1 3.5
Legacy Chip IL = 0mA, –40°C ≤ TJ ≤ 125°C 5
New Chip 5.5
Legacy Chip IL = 1mA 7 10
New Chip 10.5 15.5
Legacy Chip IL = 1mA, –40°C ≤ TJ ≤ 125°C 15
New Chip 18.5
Legacy Chip IL = 10mA 40 60
New Chip 95 115
Legacy Chip IL = 10mA, –40°C ≤ TJ ≤ 125°C 90
New Chip 148
Legacy Chip IL = 50mA 120 150
New Chip 120 145
Legacy Chip IL = 50mA, –40°C ≤ TJ ≤ 125°C 225
New Chip 184
IGND Ground Pin Current Legacy Chip IL = 0mA 60 95 µA
New Chip 55 70
Legacy Chip IL = 0mA, –40°C ≤ TJ ≤ 125°C 125
New Chip 90
Legacy Chip IL = 1mA 80 110
New Chip 70 82
Legacy Chip IL = 1mA, –40°C ≤ TJ ≤ 125°C 170
New Chip 105
Legacy Chip IL = 10mA 120 220
New Chip 150 188
Legacy Chip IL = 10mA, –40°C ≤ TJ ≤ 125°C 460
New Chip 220
Legacy Chip IL = 50mA 320 600
New Chip 350 420
Legacy Chip IL = 50mA, –40°C ≤ TJ ≤ 125°C 1200
New Chip 600
Legacy Chip VON/OFF < 0.18V, VIN ≤ 4.3V, –40°C ≤ TJ ≤ 125°C 0.01 1
New Chip 0.2 0.8
New Chip VON/OFF < 0.18V, VIN = 16V, –40°C ≤ TJ ≤ 125°C 2.5
IADJ ADJ Pin Bias Current Legacy Chip 1 mA ≤ IL ≤ 50 mA 150 350 nA
New Chip 0.35 30
VUVLO+ Rising bias supply UVLO New Chip VIN rising, –40°C ≤ TJ ≤ 125°C 2.2 2.4 V
VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 2.07
VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130
VON/OFF ON/OFF input voltage Legacy Chip High = O/P ON 1.6 1.4 V
Low = O/P OFF 0.55 0.18
New Chip High = O/P ON 1.6 0.82
Low = O/P OFF 0.7 0.18
ION/OFF ON/OFF input Current Legacy Chip VON/OFF = 0 0.01 –1 µA
VON/OFF = 5V 5 15
New Chip VON/OFF = 0 –0.35 –0.7
VON/OFF = 5V 0.008 0.5
IO(PK) Peak Output Current Legacy Chip VOUT ≥ VO(NOM) – 5% 100 150 mA
New Chip 130 150
IO(MAX) Short Circuit Current Legacy Chip RL = 0 (Steady State) 150
New Chip 160
en Output Noise Voltage (RMS) Legacy Chip BW = 300 Hz to 50 kHz, COUT = 10µF 160 µV
New Chip BW = 300 Hz to 50 kHz, COUT = 2.2µF 160
BW = 10 Hz to 100 kHz, COUT = 2.2µF 220
ΔVOUT/ΔVIN Ripple Rejection Legacy Chip f = 1 kHz, COUT = 10µF 68 dB
New Chip f = 1 kHz, COUT = 2.2µF 68
f = 100 kHz, COUT = 2.2µF 45
Tsd(shutdown) Thermal shutdown threshold New Chip Shutdown, temperature increasing 170 °C
Tsd(reset) Reset, temperature decreasing 150