8.3.1 Data Format

The LMP93601 provides 16 bits of data in binary two's complement format. The positive full-scale input produces an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale (FS). Table 2 summarizes the ideal output codes for different input signals.

8.3.2 Transfer Function

The ADC output code in decimal is given by the relation:

Equation 1.

8.3.3 Input Routing Mux

The LMP93601 offers 5 differential input channel configurations for its 3 differential input pairs:

• For 1-ch system: One of the 3 channels, Ch1, Ch2, or Ch3 is enabled
• For 2-ch system: Ch1 & Ch2 are enabled
• For 3-ch system: Ch1, Ch2, Ch3 are enabled

8.3.4 Programmable Gain Amplifier

The PGA provides a high input impedance to interface with signal sources that may have relatively high output impedance, such as thermopiles. The Programmable Gain amplifier gain can be programmed to 16, 32 64, and 128 V/V.

The maximum differential input voltage (Vdiff) of the PGA is ±64 mV when the programmed analog gain is 16 V/V. With analog gain programmed to 64V/V the maximum differential input voltage of the PGA is ±16 mV.

The input common mode voltage range of the PGA is AGND+0.3+Vdiff*Gain/2 to AVDD-1.40-Vdiff*Gain/2.

The PGA also has an EMIRR filter incorporated. The EMIRR filter is a single pole roll off providing enhanced noise immunity for unwanted RF signals.

8.3.5 PGA Bypass Mode

The PGA can be bypassed to access the 16 bit Delta-Sigma modulator directly. This mode results in a typical gain of 1 V/V at a supply current of typically 230 µA. The input common mode range in the PGA-bypass mode is rail to rail and the maximum differential input voltage that can be applied to the Delta-Sigma modulator is ± 1.2 Vpp differential. The typical noise at 1057 SPS is 20 uVrms. Typical input impedance in the PGA bypass mode is 1.3 MΩ//7 pF. In the PGA-bypass mode, the PGA and overrange detectors are disabled. To access the PGA-bypass mode the following SPI write sequence must be followed in this exact order:

To exit the PGA-bypass mode, a reset is required, either via the RSTB or SPI. Failure to follow this exact sequence may result in the device becoming unresponsive, thereby requiring a reset, either via the RSTB or SPI.

8.3.6 Over-Range Detection

The PGA has over-range detection and when signals are outside the minimum or maximum allowed signal, an out of range condition will be reported as “0x7FFF” for the corresponding channel. A status register provides further details of the out of range condition. The overrange detectors are at the output of the PGA and check for five conditions:

• PGA positive output low
• PGA negative output low
• PGA positive output high
• PGA negative output high
• PGA differential output high

The “output high” overrange detectors typically trip at AVDD-1.28 V. Both “output low” overrange detectors typically trip at 0.11 V and the differential overrange detector is typically at +1.22 and -1.22 V differential.

For example, if the input common mode is below 0.11 V and a zero differential voltage (shorted input) is applied, both the PGA positive and PGA negative “output low” detectors would trip. Likewise, if the input common mode is over AVDD-1.28 and a zero differential voltage (shorted input) is applied, both the PGA positive and PGA negative “output high” detectors would trip.

For the differential output high detector to trip, the output of the PGA has to be greater than 1.22 V or less than –1.22 V. At a gain of 64, this would translate to an input referred differential voltage of Vdiff = 1.22/64 = 19 mV

8.3.7 Analog-To-Digital Converter (ADC)

The 16 bit Sigma Delta Modulator (SDM) takes the output signal of the PGA and converts this signal into a high resolution bit stream that is further processed by the digital filters. The 2.4 V reference for the SDM is internally generated and requires a high-performance, low ESR (<0.1 Ω), and Low ESL(<1nH) 1uF (±10%) external bypass capacitor for optimal performance on the XCAP1 pin. This reference should not be used to drive external circuitry.

The SDM clock uses a divided-down external clock (XCLK).

8.3.8 Programmable Digital Filters

A programmable digital filter behind the SDM reconstructs the signal from the SDM output bit stream. The filter consists of programmable filter stages. Each of the stages further filters and decimates the bit stream so that the data rate and bandwidth of the signal is reduced and at the same time the resolution is enhanced.

An example of the filter response when programmed for 265, 530, 1057 or 1326 SPS is shown in Figure 16.

Figure 16. Bandwidth and Module Noise Performance

8.3.9 Common Mode Voltage Generator

The common mode reference generator (VCM) provides an AVDD/3 reference. It can drive a 100nF (±10%) external capacitance with typical ESR/ESL of 0.1 Ω and 1 nH. It can also be used to drive guard traces placed around the input PCB traces to reduce PCB leakage currents to the inputs. The VCM can be disabled with the Reference Enable register. In case the VCM is disabled, an external common mode voltage that tracks the common mode of the input channel(s) needs to be connected to the VCM pin to function as a reference for the over-range detection circuitry. In case the VCM is disabled, it is recommended to add an external 10 kΩ series resistor.

8.3.10 Low Drop-Out Regulator (LDO)

The on chip LDO generates 1.2V for the digital core. A 100nF (+/-10%) external capacitance with low ESR/ESL (typical 0.1 ohm and 1 nH) is required on the XCAP2 pin to provide adequate supply bypass for the internal digital core. The LDO should not be used to drive external circuitry.

8.3.11 External Clock

The LMP93601 does not have an internal oscillator and needs an external clock, XCLK. The XCLK needs to be running all the time when the LMP93601 is operating. The SYNC, DRDYB, and RSTB are synchronous to XCLK. The LMP93601 operating range for XCLK is 3.6 to 4.4 MHz.

8.3.12 Operating Modes

The LMP93601 can be programmed to convert data in continuous-time or single shot modes.

8.3.13 Data Ready Function (DRDYB)

DRDYB is an active low output signal. It is asserted when new data is ready to be read and should be used by the MCU for data capturing.

When DRDYB is asserted, the MCU can capture the data any time before the next DRDYB is asserted. The time is defined as 1/ODR. Please note that if data is not read within the time period, it will be over-written internally in the LMP93601 by the new data.

For DRDYB de-assertion, it is normally cleared by a data read. In the following example: it is de-asserted on the 14^th SCLK rising edge.

If data has not been read when the new data is about to be ready, DRDYB will be de-asserted for 15 XCLK periods (defined as t_DRDYB) so that LMP93601 can re-assert the DRDYB. Once this happens, the µC should wait for the next DRDYB assertion before issuing an SPI read protocol.

DRDYB assertion and de-assertion is synchronous to XCLK and SCLK respectively in normal operation.

Figure 17. DRDYB Behavior for A Complete Read Operation

Figure 18. DRDYB Behavior for an Incomplete Read Operation

8.3.14 Synchronous Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) interface allows access to the control registers of the LMP93601. The serial interface is a generic 4-wire synchronous interface compatible with SPI type of interfaces used on many microcontrollers and DSP controllers. A typical serial interface access cycle is exactly 16 bits long, which includes an 8-bit command field (R/WB + 7-bit address) to provide a maximum of 128 direct access addresses, and an 8-bit data field.

LMP93601’s SCLK can be in either idle high or idle low state when CSB is de-asserted. The first incoming data on the SCLK rising edge, and all incoming data at SDI is captured on the SCLK rising edge. Outgoing data is sourced at SDO on the SCLK falling edge and the MCU can capture data from the LMP93601 on the SCLK rising edge.

8.3.15 Power Management Mode; Standby, Conversion and Shutdown

The device can be placed in Standby and Conversion mode via the SPI. In Conversion mode, the ADC and PGA are operating and converting data. In Standby mode the PGA and ADC are disabled and not converting data. In Standby mode the contents of the registers are unaffected, and there is a drastic power reduction. Only the internal reference, LDO, VCM driver and the digital are on.

The reaction time going from Standby mode to Conversion mode is approximately 100 µs.

The LMP93601 can be put in shutdown mode by taking the PWDNB pin low. In shutdown mode, all internal circuitry is disabled and no register settings are maintained. The power consumption is very low (< 0.1 uA). Releasing the PWDNB (taking it high) will “wake up” the device and it will return to the default Standby mode. Wake up time from shutdown can be up to 10 ms.

8.3.16 Power-On Sequence and Reset (POR) Function

An internal power on reset is generated after both the internal LDO (to supply the internal digital) and IOVDD reach valid values. The internal LDO will reach stable values only after the AVDD has reached at least 2.7 V.

The device should be powered up with AVDD enabled and stabilized first, then the IOVDD. This allows the device to start in the default power up state and ensures that the internal power on reset is generated after both the internal LDO (to supply the internal digital) and IOVDD reach valid values. The internal LDO will reach stable values only after the AVDD has reached at least 2.7 V for 1 ms. Alternatively, AVDD and IOVDD can be connected together, but this can result in an erroneous brown-out condition being reported when the ramp time of the supplies is slower than 0.1 V/ms. For example, if the AVDD = IOVDD are linearly ramped from 0 to 3.3 V in longer than 330 µs, the brown could possibly trigger and be logged in the status register and the first conversion result could read ‘7FFF’. To avoid this erroneous brown-out report, three alternative solutions are available:

1. After the supplies are stable, reset the part (either with the RSTB pin or with a soft reset via SPI). After this reset, the part can be programmed and used as intended.
2. Or, after the supplies are stable, program the part as desired, but before initiating the first conversion, read back the status register(s) of the enabled channel(s) to clear the erroneous brown-out status.
3. Or, wait supplying the XCLK to the part until after the supplies are stable

8.3.17 Brown-Out Detection Function

A brown-out detection circuit monitors the AVDD. It triggers an alarm only when AVDD falls below ~2.55 V and stays below 2.55 V for more than 16 fxclk cycles. The brown-out detection has a hysteresis of ~65 mV. The alarm will result in “0x7FFF” data and the appropriate channel status register(s) can be read to decode the alarm. The brown-out error function can be masked via SPI with the “alarm mask” register.

8.3.18 Reset Function

The device can be reset to the default (Standby) state via the SPI or taking the RSTB pin low. The reaction time from the reset (either via SPI or RSTB pin) to the device getting to Standby mode is on the order of 100 µs. See Table 6

8.4.1 Single-Shot Mode

In Single Shot mode each conversion is triggered by a Start Trigger from the microcontroller unit (MCU) to the LMP93601 by pulsing the SYNC pin or via a start SPI command (SYNC is recommended for exact timing control). After the LOCK bit is set, the external µC should wait 3 XCLK cycles before it sends a start trigger. This is to allow the internal synchronizer enough time to synchronize the SPI write of the LOCK bit into the XCLK domain. This assumes the analog has already settled (otherwise, allow ~100 µs to go from standby to conversion mode).

The SYNC has typical setup/hold time of 20 ns with respect to XCLK, as shown in Figure 19.

Figure 19. Single Shot Sync Setup/Hold Time

See Figure 20 for details regarding the Single Shot Flow Chart.

Figure 20. Single Shot Flow Chart

8.4.2 Continuous Mode

In Continuous mode the LMP93601 only requires a single Start Trigger to start. The Start Trigger can start either by a SYNC or a Start command via the SPI (SYNC is recommended). After the LOCK bit is set, the external MCU should wait 3 XCLK cycles before it sends a start trigger. This allows the internal synchronizer enough time to synchronize the SPI write of the LOCK bit into the XCLK domain. This assumes the analog has already settled (else allow ~100 µs to go from standby to conversion mode).

It will convert all enabled channels without requiring another Start Trigger. Figure 21 shows the Continuous Mode Flow Chart.

Figure 21. Continuous Mode Flow Chart

8.5.1 Window to Capture Data and Status

SPI Protocols can be asynchronous to XCLK. Data and status read can only happen between the consecutive DRDYB falling edges. For example, after DRDYB is asserted by the LMP93601, the MCU has to finish reading all data before DRDYB is asserted again.

For best performance in continuous acquisition mode, it is recommended to read the data within 70 µs after DRDYB is asserted in order to keep the SPI activity during conversion to a minimum.

Figure 22. Channel Data Transfer Timing Diagram

Figure 23. Channel Data Transfer Timing Diagram

8.5.2 Single Byte Access

WRITE: A single byte write access is a total of 16 SCLK periods during CSB assertion. Incoming data is captured on the rising edge of the SCLK. A command byte consists of an R/W bit and a 7-bit address field and R/W = 0 for write protocols.

Figure 24. Single Byte Write Access

READ: Similar to a write, the LMP93601 captures incoming data on the SCLK rising edge. After the 8th rising edge, the LMP93601 output data is sourced on the SCLK falling edge and the MCU should capture it on the rising edge. R/W = 1 for read protocols.

Figure 25. Single Byte Read Access