SNVS639G December   2009  – December 2015 LM21305

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Synchronous DC-DC Switching Converter
      2. 8.3.2  Peak Current-Mode Control
      3. 8.3.3  Switching Frequency Setting and Synchronization
      4. 8.3.4  Light-Load Operation
      5. 8.3.5  Precision Enable
      6. 8.3.6  Device Enable, Soft-Start, and Pre-Bias Startup Capability
      7. 8.3.7  Peak Current Protection and Negative Current Limiting
      8. 8.3.8  PGOOD Indicator
      9. 8.3.9  Internal Bias Regulators
      10. 8.3.10 Minimum On-Time Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overvoltage and Undervoltage Handling
      2. 8.4.2 Undervoltage Lockout (UVLO)
      3. 8.4.3 Thermal Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Setting the Output Voltage
        2. 9.2.2.2  Calculating the Duty Cycle
        3. 9.2.2.3  Input Capacitors
        4. 9.2.2.4  AVIN Filter
        5. 9.2.2.5  Switching Frequency Selection
        6. 9.2.2.6  Filter Inductor
        7. 9.2.2.7  Output Capacitor
        8. 9.2.2.8  Efficiency Considerations
        9. 9.2.2.9  Load Current Derating When Duty Cycle Exceeds 50%
        10. 9.2.2.10 Control Loop Compensation
        11. 9.2.2.11 Compensation Components Selection
        12. 9.2.2.12 Plotting the Loop Gain
        13. 9.2.2.13 High Frequency Considerations
        14. 9.2.2.14 Bootstrap Capacitor
        15. 9.2.2.15 5V0 and 2V5 Capacitors
        16. 9.2.2.16 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Ground Plane and Thermal Design Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 PCB Layout Resources
      3. 12.2.3 Resources for Thermal PCB Design
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

see (1)(2)
MIN MAX UNIT
PVIN, AVIN, SW, EN, PGOOD to AGND −0.3 20 V
CBOOT to AGND −0.3 25 V
CBOOT to SW −0.3 5.5 V
5V0, FB, COMP, FREQ to AGND −0.3 6 V
2V5 to AGND −0.3 3 V
AGND to PGND −0.3 0.3 V
Maximum continuous power dissipation, PD-MAX(3) Internally limited
Junction temperature, TJ-MAX 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military or Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) The amount of absolute maximum power dissipation allowed in the device depends on the ambient temperature and can be calculated using the formula P = (TJ – TA) / θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high power dissipation exists, special care must be paid to thermal dissipation issues in PCB design. Internal thermal shutdown circuitry protects the device from permanent damage.
(4) In applications where high power dissipation or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part or package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin (MIL-STD-883 3015.7).

7.3 Recommended Operating Conditions

MIN MAX UNIT
PVIN to PGND, AGND 3 18 V
AVIN to PGND, AGND 3 18 V
Junction temperature −40 125 °C
Ambient temperature(4) –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) LM21305 UNIT
RSG (WQFN)
28 PINS
RθJA Junction-to-ambient thermal resistance 36.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22 °C/W
RθJB Junction-to-board thermal resistance 9.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 9.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

All typical limits apply for TJ = 25°C, and all maximum and minimum limits apply over the full operating temperature range (TJ = –40°C to +125°C). Unless otherwise specified, VIN = VPVIN = VAVIN = 12 V, VOUT = 3.3 V, IOUT = 0 A.(1)(2)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
VFB-default Feedback pin factory-default voltage 0.588 0.598 0.608 V
ΔVOUT/ΔIOUT Load regulation IOUT = 0.1 A to 5 A 0.02 %/A
ΔVOUT/ΔVIN Line regulation VPVIN = 3 V to 18 V 0.01 %/V
RDSonHS High-side switch on-resistance IDS = 5 A 44 mΩ
RDSonLS Low-side switch on-resistance IDS = 5 A 22 mΩ
ICL-HS High-side switch current limit High-side MOSFET 5.9 7 7.87 A
ICL-LS Low-side switch current limit Low-side MOSFET(3) 5.9 8 10.2 A
INEG-CL-LS Low-side switch negative current limit Low-side MOSFET –7 –4.1 –1.64 A
ISD Quiescent current, disabled VAVIN = V PVIN = 5 V 0.1 2 µA
VAVIN = V PVIN = 18 V 1 4.1
IQ Quiescent current, enabled, not switching VAVIN = V PVIN = 18 V 9 9.7 mA
IFB Feedback pin input bias current VFB = 0.598 V 1 nA
GM Error amplifier transconductance 2400 µs
AVOL Error amplifier voltage gain 65 dB
VIH-OVP OVP tripping threshold Rising threshold, percentage of VOUT 103.5% 109.5% 115%
VHYST-OVP OVP hysteresis window Percentage of VOUT –4.3%
VUVLO-HI-AVIN AVIN UVLO rising threshold 2.84 2.93 2.987 V
VUVLO-LO-AVIN AVIN UVLO falling threshold 2.66 2.73 2.83 V
VUVLO-HYS-AVIN AVIN UVLO hysteresis window 195 mV
V5V0 Internal LDO1 output voltage Measured at 5V0 pin, 1-kΩ load 4.88 V
COUT-CAP-5V0 Recommended capacitance connected to 5V0 pin Ceramic capacitor 1 µF
GENERAL (continued)
ISHORT-5V0 Short-circuit current of 5V0 pin 31 mA
V2V5 Internal LDO2 output voltage Measured at 2V5 pin, 1-kΩ load 2.47 V
COUT-CAP-2V5 Recommended capacitance connected to 2V5 pin Ceramic capacitor 100 nF
ISHORT-2V5 Short-circuit current of 2V5 pin 47 mA
VFCBOOT-D CBOOT diode forward voltage Measured from 5V0 to CBOOT at 10 mA 0.76 V
ICBOOT CBOOT leakage current VCBOOT = 5.5 V, not switching 0.65 µA
TSTARTUP-DELAY Startup time from EN high to the beginning of internal soft-start 160 µs
SS Internal soft-start 10% to 90% VFB 1.41 2.7 4.15 ms
OSCILLATOR
FOSC-NOM Oscillator frequency, nominal measured at SW pin RFRQ = 61.9 kΩ, 0.025% 695 750 795 kHz
FOSC-MAX Maximum oscillator frequency measured at SW pin RFRQ = 28.4 kΩ 1500 kHz
FOSC-MIN Minimum oscillator frequency measured at SW pin RFRQ = 167.5 kΩ 300 kHz
TOFF-MIN Minimum off-time measured at SW pin FSW = 1.5 MHz, VIN = 3.3 V, VFB = 1 V, voltage divider ratio = 3.3 50 ns
TON-MIN Minimum on-time measured at SW pin FSW = 1.5 MHz, voltage divider ratio = 1 70 ns
LOGIC
VIH-EN EN pin rising threshold 1.1 1.2 1.3 V
VHYST-EN EN pin hysteresis window 130 200 302 mV
IEN-IN EN pin input current VEN = 12 V 18 23 µA
VIH-UV-PGOOD PGOOD UV rising threshold Percentage of VOUT 87.5% 93% 97.5%
VHYST-UV-PGOOD PGOOD UV hysteresis threshold Percentage of VOUT –4.2%
IOL- PGOOD PGOOD sink current VOL = 0.2 V 3 mA
IOH- PGOOD PGOOD leakage current VOH = 18 V 460 nA
THERMAL SHUTDOWN
TSD Thermal shutdown(4) 160 °C
TSD-HYS Thermal shutdown hysteresis(4) 10 °C
(1) All limits are specified by design, test or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Capacitors: low ESR surface-mount ceramic capacitors (MLCCs) are used in setting electrical characteristics.
(3) The low-side switch current limit is ensured to be higher than the high-side current limit.
(4) Specified by design.

7.6 Typical Characteristics

VIN = 12 V, VOUT = 3.3 V, FSW = 500 kHz, TA = 25°C, L = 3.3 µH, and COUT = 100 µF (ceramic), (unless otherwise specified)
LM21305 30111137.gif
FSW = 300 kHz
Figure 1. Efficiency with PVIN = AVIN = 5 V
LM21305 30111152.gif
FSW = 500 kHz
Figure 3. Efficiency with PVIN = AVIN = 5 V
LM21305 30111139.gif
FSW = 1 MHz
Figure 5. Efficiency with PVIN = AVIN = 5 V
LM21305 30111127.gif
Figure 7. Load Regulation (% VOUT)
LM21305 30111128.gif
Figure 9. VOUT Regulation (%) vs Temperature
LM21305 30111147.gif
Figure 11. High-Side and Low-Side MOSFET RDS(on)
vs Temperature
LM21305 30111184.gif
Figure 13. Soft-Start, No Load
LM21305 30111155.gif
Figure 15. Soft-Start with 2-V Pre-Bias Voltage, No Load
LM21305 30111194.png
Figure 17. Switching Waveform with 5-A Load
LM21305 30111138.gif
FSW = 300 kHz
Figure 2. Efficiency with PVIN = AVIN = 12 V
LM21305 30111153.gif
FSW = 500 kHz
Figure 4. Efficiency with PVIN = AVIN = 12 V
LM21305 30111151.gif
FSW = 1 MHz
Figure 6. Efficiency with PVIN = AVIN = 12 V
LM21305 30111130.gif
Figure 8. Line Regulation (% VOUT)
LM21305 30111159.gif
Figure 10. Input Quiescent Current, Not Switching
LM21305 30111157.gif
Figure 12. Switching Frequency vs RFRQ
LM21305 30111192.gif
Figure 14. Soft-Start with Resistive Load
LM21305 30111193.png
Figure 16. Switching Waveform with No Load Connected (DCM Operation)
LM21305 30111145.png
Figure 18. Load Transient Response, 0.1 A to 5 A