ZHCSQ40C January   2023  – September 2023 LM2105

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 功能方框图
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and GVDD Capacitor
        2. 8.2.2.2 Select External Gate Driver Resistor
        3. 8.2.2.3 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

8.2.3 Application Curves

Figure 8-2 and Figure 8-3 show the rise times and turn-on propagation delays for the low side driver and the high side driver respectively. Likewise, Figure 8-4 and Figure 8-5 show the fall times and turn-off propagation delays. Each channel (INH, INL, GH, and GL) is labeled and displayed on the left hand of the waveforms.

The testing condition: load capacitance is 1 nF, gate resistor is 4 Ω, VDD = 12 V, fSW = 50 kHz.

GUID-20230512-SS0I-PQPP-QPJV-468CGZ8P9HCS-low.svg
CL = 1 nF RG = 4 Ω VGVDD = 12 V fSW = 50 kHz
Figure 8-2 GL Rise Time and INL to GL Turn-on Propagation Delay
GUID-20230512-SS0I-JNZQ-RQX0-RBK7PPLGJZ2M-low.svg
CL = 1 nF RG = 4 Ω VDD = 12 V fSW = 50 kHz
Figure 8-4 GL Fall Time and INL to GL Turn-off Propagation Delay
GUID-20230512-SS0I-GLZG-CCDF-CRRPWZHKDSNZ-low.svg
CL = 1 nF RG = 4 Ω VGVDD = 12 V fSW = 50 kHz
Figure 8-3 GH Rise Time and INH to GH Turn-on Propagation Delay
GUID-20230512-SS0I-KXKP-HFCH-RKFNG8DQT4KD-low.svg
CL = 1 nF RG = 4 Ω VDD = 12 V fSW = 50 kHz
Figure 8-5 GH Fall Time and INH to GH Turn-off Propagation Delay