10.1 Layout Guidelines

The DRV421 unique, integrated fluxgate has a very high sensitivity to magnetic fields in order to enable design of a closed-loop current sensor with best-in-class precision and linearity. Observe proper PCB layout techniques because any current-conducting wire in the direct vicinity of the DRV421 generates a magnetic field that may distort measurements. Common passive components and some PCB plating materials contain ferromagnetic materials that are magnetizable. For best performance, use the following layout guidelines:

• Route current conducting wires in pairs: route a wire with an incoming supply current next to, or on top of its return current path. The opposite magnetic field polarity of these connection cancel each other. To facilitate this layout approach, the DRV421 positive and negative supply pins are located next to each other.
• Route the compensation coil connections close to each other as a pair to reduce coupling effects.
• Route currents parallel to the fluxgate sensor sensitivity axis as shown in Figure 71. As a result, magnetic fields are perpendicular to the fluxgate sensitivity, and have limited impact.
• Vertical current flow (for example, through vias) generates a field in the fluxgate-sensitive direction. Minimize the number of vias in vincinity of the DRV421.
• Place all passive components (for example, decoupling capacitors and the shunt resistor) outside of the portion of the PCB that is inserted into the magnetic core gap. Use nonmagnetic components to prevent magnetizing effects.
• Do not use PCB trace finishes using nickel-gold plating because of the potential for magnetization.
• Connect all GND pins to a local ground plane.

Ferrite beads in series to the power-supply connection reduce interaction with other circuits powered from the same supply voltage source. However, to prevent influence of the magnetic fields if ferrite beads are used, do not place them next to the DRV421.

The reference output (REFOUT pin) refers to GND. Use a low-impedance and star-type connection to reduce the driver current and the fluxgate sensor current modulating the voltage drop on the ground track. The REFOUT and VOUT outputs are able to drive some capacitive load, but avoid large direct capacitive loading because of increased internal pulse currents. Given the wide bandwidth of the shunt sense amplifier, isolate large capacitive loads with a small series resistor.

Solder the exposed PowerPAD, on the bottom of the package to the ground layer because the PowerPAD is internally connected to the substrate that must be connected to the most-negative potential.

Figure 71 illustrates a generic layout example that highlights the placement of components that are critical to the DRV421 performance. For specific layout examples, see SLOU409, DRV421EVM Users Guide, and TIDUA92, TIPD196 Design Guide.

10.2 Layout Example

Figure 71. Generic Layout Example (Top View)