ZHCSLT4D 数据表 | 德州仪器 TI.com.cn

ZHCSLT4D April 2019 – December 2023 DLP660TE

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FYG|350
- MCPS002

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zhcslt4d_oa

5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by recommended operating conditions . No level of performance is implied when operating the device above or below the limits.

		MIN	NOM	MAX	UNIT
Voltage Supply
V_CC	LVCMOS logic supply voltage⁽¹⁾	1.65	1.8	1.95	V
V_CCI	LVCMOS LVDS Interface supply voltage⁽¹⁾	1.65	1.8	1.95	V
V_OFFSET	Mirror electrode and HVCMOS voltage⁽¹⁾⁽²⁾	9.5	10	10.5	V
V_BIAS	Mirror electrode voltage⁽¹⁾	17.5	18	18.5	V
V_RESET	Mirror electrode voltage⁽¹⁾	–14.5	–14	–13.5	V
\|V_CC – V_CCI\|	Supply voltage delta (absolute value)⁽³⁾		0	0.3	V
\|V_BIAS – V_OFFSET\|	Supply voltage delta (absolute value)⁽⁴⁾			10.5	V
\|V_BIAS – V_RESET\|	Supply voltage delta (absolute value)⁽⁵⁾			33	V
LVCMOS Interface
V_IH(DC)	DC input high voltage⁽⁶⁾	0.7 × V_CC		V_CC + 0.3	V
V_IL(DC)	DC input low voltage⁽⁶⁾	–0.3		0.3 × V_CC	V
V_IH(AC)	AC input high voltage^⁽⁶⁾	0.8 × V_CC		V_CC + 0.3	V
V_IL(AC)	AC input low voltage⁽⁶⁾	–0.3		0.2 × V_CC	V
t_PWRDNZ	PWRDNZ pulse width⁽⁷⁾	10			ns
SCP Interface
ƒ_SCPCLK	SCP clock frequency⁽⁸⁾			500	kHz
t_{SCP_PD}	Propagation delay, clock to Q, from rising edge of SCPCLK to valid SCPDO⁽⁹⁾	0		900	ns
t_{SCP_NEG_ENZ}	Time between the falling edge of SCPENZ and the first rising edge of SCPCLK	2			µs
t_{SCP_POS_ENZ}	Time between the falling edge of SCPCLK and the rising edge of SCPENZ	2			µs
t_{SCP_DS}	SCPDI clock setup time (before SCPCLK falling edge)⁽⁹⁾	800			ns
t_{SCP_DH}	SCPDI hold time (after SCPCLK falling edge)⁽⁹⁾	900			ns
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	2			µs
LVDS Interface
ƒ_CLOCK	Clock frequency for LVDS interface (all channels), DCLK⁽¹⁰⁾			400	MHz
\|V_ID\|	Input differential voltage (absolute value)⁽¹¹⁾	150	300	440	mV
V_CM	Common mode voltage⁽¹¹⁾	1100	1200	1300	mV
V_LVDS	LVDS voltage⁽¹¹⁾	880		1520	mV
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			2000	ns
Z_IN	Internal differential termination resistance	80	100	120	Ω
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long-term operational⁽¹²⁾⁽¹³⁾⁽¹⁴⁾⁽¹⁵⁾⁽²²⁾	10		40 to 70	°C
T_ARRAY	Array temperature, short-term operational, 500-hr max⁽¹³⁾⁽¹⁶⁾	0		10	°C
T_WINDOW	Window temperature – operational⁽¹⁷⁾			85	°C
\|T_DELTA\|	Absolute temperature delta between any point on the window edge and the ceramic test point TP1⁽¹⁸⁾			14	°C
T_{DP -AVG}	Average dew point temperature (non-condensing)⁽¹⁹⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽²⁰⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	Months
ILL_θ	Illumination marginal ray angle⁽²¹⁾			55	°
SOLID STATE ILLUMINATION
ILL_UV	Illumination power < 410 nm⁽¹²⁾⁽²³⁾			10	mW/cm²
ILL_VIS	Illumination power ≥ 410 nm and ≤ 800 nm⁽²²⁾⁽²³⁾			22	W/cm²
ILL_IR	Illumination power > 800 nm⁽²³⁾			10	mW/cm²
ILL_BLU	Illumination power ≥ 410 nm and ≤ 475 nm⁽²²⁾⁽²³⁾			7	W/cm²
ILL_BLU1	Illumination power ≥ 410 nm and ≤ 440 nm⁽²²⁾⁽²³⁾			1.1	W/cm²
LAMP ILLUMINATION
ILL_UV	Illumination power < 395 nm⁽¹²⁾⁽²³⁾			2	mW/cm²
ILL_VIS	Illumination power ≥ 395 nm and ≤ 800 nm⁽²²⁾⁽²³⁾			18	W/cm²
ILL_IR	Illumination power > 800 nm⁽²³⁾			10	mW/cm²

(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.

(2) VOFFSET supply transients must fall within specified max voltages.

(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. See Section 8, Figure 8-1, and Table 8-1.

(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. See Section 8, Figure 8-1, and Table 8-1.

(5) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit. See Section 8, Figure 8-1, and Table 8-1.

(6) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B.Tester Conditions for VIH and VIL.

Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% – 80%)
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% – 20%)

(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.

(8) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(9) See Figure 5-2.

(10) See LVDS Timing Requirements in Section 5.8 and Figure 5-6.

(11) See Figure 5-5 LVDS Waveform Requirements.

(12) Simultaneous exposure of the DMD to the maximum Section 5.4 for temperature and UV illumination reduces device lifetime.

(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 6-1 and the package thermal resistance using the calculation in Section 6.6.

(14) Per Figure 5-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 6.8 for a definition of micromirror landed duty cycle.

(15) Long-term is defined as the usable life of the device.

(16) Short-term is the total cumulative time over the useful life of the device.

(17) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(18) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 6-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 6-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.

(19) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.

(20) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(21) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including pond of micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document and may negatively affect lifetime.

(22) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

(23) To calculate, see the Micromirror Power Density Calculation.

Figure 5-1 Max Recommended Array Temperature—Derating Curve