ZHCSLT4D April   2019  – December 2023 DLP660TE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions—Test Pads
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Capacitance at Recommended Operating Conditions
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Optical Interface and System Image Quality
        1. 6.5.1.1 Numerical Aperture and Stray Light Control
        2. 6.5.1.2 Pupil Match
        3. 6.5.1.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 DMD Die Temperature Sensing
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
        1. 9.2.3.1 Voltage Signals
  11. 10Device and Documentation Support
    1. 10.1 第三方产品免责声明
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
      1. 10.3.1 Related Documentation
    4. 10.4 接收文档更新通知
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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5.8 Timing Requirements

MIN NOM MAX UNIT
SCP(1)
tr Rise time 20% to 80% reference points 30 ns
tf Fall time 80% to 20% reference points 30 ns
LVDS(2)
tr Rise slew rate 20% to 80% reference points 0.7 1 V/ns
tf Fall slew rate 80% to 20% reference points 0.7 1 V/ns
tC Clock Cycle DCLK_A, LVDS pair 2.5 ns
tC Clock Cycle DCLK_B, LVDS pair 2.5 ns
tC Clock Cycle DCLK_C,LVDS pair 2.5 ns
tC Clock Cycle DCLK_D, LVDS pair 2.5 ns
tW Pulse Width DCLK_A LVDS pair 1.19 1.25 ns
tW Pulse Width DCLK_B LVDS pair 1.19 1.25 ns
tW Pulse Width DCLK_C LVDS pair 1.19 1.25 ns
tW Pulse Width DCLK_D LVDS pair 1.19 1.25 ns
tSu Setup Time D_A(15:0) before DCLK_A, LVDS pair 0.325 ns
tSu Setup Time D_B(15:0) before DCLK_B, LVDS pair 0.325 ns
tSu Setup Time D_C(15:0) before DCLK_C, LVDS pair 0.325 ns
tSu Setup Time D_D(15:0) before DCLK_D, LVDS pair 0.325 ns
tSu Setup Time SCTRL_A before DCLK_A, LVDS pair 0.325 ns
tSu Setup Time SCTRL_B before DCLK_B, LVDS pair 0.325 ns
tSu Setup Time SCTRL_C before DCLK_C, LVDS pair 0.325 ns
tSu Setup Time SCTRL_D before DCLK_D, LVDS pair 0.325 ns
th Hold Time D_A(15:0) after DCLK_A, LVDS pair 0.145 ns
th Hold Time D_B(15:0) after DCLK_B, LVDS pair 0.145 ns
th Hold Time D_C(15:0) after DCLK_C, LVDS pair 0.145 ns
th Hold Time D_D(15:0) after DCLK_D, LVDS pair 0.145 ns
th Hold Time SCTRL_A after DCLK_A, LVDS pair 0.145 ns
th Hold Time SCTRL_B after DCLK_B, LVDS pair 0.145 ns
th Hold Time SCTRL_C after DCLK_C, LVDS pair 0.145 ns
th Hold Time SCTRL_D after DCLK_D, LVDS pair 0.145 ns
LVDS(2)
tSKEW Skew Time Channel B relative to Channel A(3)(4), LVDS pair –1.25 +1.25 ns
tSKEW Skew Time Channel D relative to Channel C(5)(6), LVDS pair –1.25 +1.25 ns
(1) See Figure 5-3 for Rise Time and Fall Time for SCP.
(2) See Figure 5-5 for Timing Requirements for LVDS.
(3) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).
(4) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).
(5) Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and D_CP(15:0).
(6) Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and D_DP(15:0).
GUID-624D8A22-ECB9-4977-9D21-F7FDA1CDAB4E-low.gif Figure 5-2 SCP Timing Requirements

See Section 5.4 for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications.

GUID-20220524-SS0I-01TK-PCDT-MBQ3X9LXVW3Z-low.svg Figure 5-3 SCP Requirements for Rise and Fall

See Section 5.8 for tr and tf specifications and conditions.

GUID-613F4BBD-52E6-47FB-829B-17144F1B170F-low.gif Figure 5-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be considered. System designers use IBIS or other simulation tools to correlate the timing reference load to a system environment.

GUID-20200901-CA0I-K2BZ-XB7J-1FNKJGHBFDSJ-low.gif Figure 5-5 LVDS Waveform Requirements
Equation 1. GUID-86B70B5E-DEAE-4ED5-B3F9-D4596C9C56FE-low.gif
Equation 2. GUID-CB0A55B8-52F7-4156-BD0E-A21B0595BED6-low.gif

See Section 5.4 for VCM, VID, and VLVDS specifications and conditions.

GUID-20200901-CA0I-9VF9-KWZT-HKTWBJMWNTHV-low.gif Figure 5-6 Timing Requirements

See Section 5.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(0:?) and D_N(0:?).