ZHCSTJ0 October   2023 DLP651LE

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  System Mounting Interface Loads
    9. 6.9  Micromirror Array Physical Characteristics
    10. 6.10 Micromirror Array Optical Characteristics
    11. 6.11 Window Characteristics
    12. 6.12 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Optical Interface and System Image Quality Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill
    5. 7.5 Micromirror Array Temperature Calculation
    6. 7.6 Micromirror Power Density Calculation
    7. 7.7 Window Aperture Illumination Overfill Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
      1. 9.2.1 Layers
      2. 9.2.2 Impedance Requirements
      3. 9.2.3 Trace Width, Spacing
  11. 10Power Supply Recommendations
    1. 10.1 DMD Power Supply Power-Up Procedure
    2. 10.2 DMD Power Supply Power-Down Procedure
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
  • FYM|149
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Timing Requirements

Over Recommended Operating Conditions (unless otherwise noted).
PARAMETER DESCRIPTION SIGNAL MIN TYP MAX UNIT
LVDS(1)
tC Clock cycle duration for DCLK_A LVDS 3.03 ns
tC Clock cycle duration for DCLK_B LVDS 3.03 ns
tW Pulse duration for DCLK_A LVDS 1.36 1.52 ns
tW Pulse duration for DCLK_B LVDS 1.36 1.52 ns
tSU Setup time for D_A(15:0) before DCLK_A LVDS 0.35 ns
tSU Setup time for D_A(15:0) before DCLK_B LVDS 0.35 ns
tSU Setup time for SCTRL_A before DCLK_A LVDS 0.35 ns
tSU Setup time for SCTRL_B before DCLK_B LVDS 0.35 ns
tH Hold time for D_A(15:0) after DCLK_A LVDS 0.35 ns
tH Hold time for D_B(15:0) after DCLK_B LVDS 0.35 ns
tH Hold time for SCTRL_A after DCLK_A LVDS 0.35 ns
tH Hold time for SCTRL_B after DCLK_B LVDS 0.35 ns
tSKEW Channel B relative to Channel A(2)(3) LVDS –1.51 1.51 ns
(1) See Timing Requirements for timing requirements for LVDS.
(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0)
(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0)
GUID-C318DBBF-7FC8-49F3-89B3-91A1F151A4BF-low.gif Figure 6-3 SCP Timing Requirements

See Recommended Operating Conditions for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications.

See Recommended Operating Conditions for tr and tf specifications and conditions.

GUID-DAD34A2D-9240-4E7C-90BE-EA2A2D6B9ECC-low.gif
Not to scale.
Refer to the Timing Requirements.
Refer to the Pin Functions for list of LVDS pins and SCP pins.
Figure 6-4 Rise Time and Fall Time
GUID-7E9964D4-747B-4934-82F1-2769E1D65FA5-low.gif Figure 6-5 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. See Test Load Circuit for Output Propagation Measurement.

GUID-6B13F334-13EE-42E5-856D-439E4969B872-low.gif Figure 6-6 LVDS Waveform Requirements

See Recommended Operating Conditions for VCM, VID, and VLVDS specifications and conditions.

GUID-A1F030B0-6D68-4592-8A85-42673D3548C5-low.gif Figure 6-7 Timing Requirements

See Timing Requirements for timing requirements and LVDS pairs per channel (bus) defining D_P(0:x) and D_N(0:x).