ZHCSN33B November   2017  – February 2023 DLP550JE

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Power Interface
      2. 7.2.2 Timing
    3. 7.3 Optical Interface and System Image Quality Considerations
      1. 7.3.1 Numerical Aperture and Stray Light Control
      2. 7.3.2 Pupil Match
      3. 7.3.3 Illumination Overfill
    4. 7.4 Micromirror Array Temperature Calculation
      1. 7.4.1 Micromirror Array Temperature Calculation
    5. 7.5 Micromirror Landed-on/Landed-Off Duty Cycle
      1. 7.5.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.5.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.5.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.5.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power-Up and Power-Down Procedures
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 支持资源
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.
MINNOMMAXUNIT
VOLTAGE SUPPLY
VCCSupply voltage for LVCMOS core logic#DLPS10137843.03.33.6V
VCCISupply voltage for LVDS receivers#DLPS10137843.03.33.6V
VOFFSETMirror Electrode and HVCMOS voltage#DLPS1013784#DLPS10189108.258.58.75V
VMBRSTMicromirror clocking pulse voltages#DLPS1013784–2726.5V
|VCCI–VCC|Supply voltage delta (absolute value)#DLPS10192200.3V
LVCMOS INTERFACE
VIHHigh level input voltage1.72.5VCC + 0.3V
VILLow level input voltage–0.30.7V
IOHHigh level output current at VOH = 2.4 V–20mA
IOLLow level output current at VOL = 0.4 V15mA
tPWRDNZPWRDNZ pulse width#DLPS101205410ns
SCP INTERFACE
fSCPCLKSCP clock frequency#T4989946-550500kHz
tSCP_PDPropagation delay, clock to Q, from rising-edge of SCPCLK to valid SCPDO#T4989946-200900ns
tSCP_DSSCPDI clock setup time (before SCPCLK falling-edge)#T4989946-20800ns
tSCP_DHSCPDI hold time (after SCPCLK falling-edge)#T4989946-20900
tSCP_NEG_ENZTime between falling-edge of SCPENZ and the first rising-edge of SCPCLK1us
tSCP_POS_ENZTime between falling-edge of SCPCLK and the rising-edge of SCPENZ1us
tSCP_PW_ENZSCPENZ inactive pulse width (high level)11/fSCPCLK
tr_SCPRise time for SCP signals200ns
tfPFall time for SCP signals200ns
LVDS INTERFACE
fCLOCKClock frequency for LVDS interface (all channels), DCLK#T4989946-34320330MHz
|VID|Input differential voltage (absolute difference)#T4989946-21100400600mV
VCMCommon mode voltage#T4989946-211200mV
VLVDSLVDS voltage#T4989946-2102000mV
trRise time (20% to 80%)100400ps
trFall time (80% to 20%)100400ps
tLVDS_RSTZTime required for LVDS receivers to recover from PWRDNZ10ns
ZINInternal differential termination resistance95105Ω
ENVIRONMENTAL
TARRAYArray temperature, long-term operational#DLPS1014991 #DLPS1018123 #T4989946-181040 to 70#T4989946-1°C
Array temperature, short-term operational#DLPS1018123#T4989946-19010°C
TWINDOWWindow temperature – operational#DLPS101630185°C
T|DELTA |Absolute temperature delta between any point on the window edge and the ceramic test point TP1#T4989946-2226°C
TDP-AVGAverage dew point temperature (non-condensing)#DLPS101939828°C
TDP-ELRElevated dew point temperature range (non-condensing)#DLPS10136972836°C
CTELRCumulative time in elevated dew point temperature range24Months
ILLUVIllumination wavelengths < 395 nm#DLPS10149910.682.00mW/cm2
ILLVISIllumination wavelengths between 395 nm and 800 nmThermally limitedmW/cm2
ILLIRIllumination wavelengths > 800 nm10mW/cm2
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. See GUID-783C8A87-C319-45F0-8ED5-D542F5788D8C.html#GUID-783C8A87-C319-45F0-8ED5-D542F5788D8C.
(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(5) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Simultaneous exposure of the DMD to the maximum #GUID-4099E5F6-AAA6-418E-9C70-AB9F6B9ED0B7 for temperature and UV illumination reduces device lifetime.
(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 and the package thermal resistance using the calculation in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.
(11) Long-term is defined as the average over the usable life.
(12) Per #DLPS1019579, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See GUID-1F08C864-8C95-4839-BD9C-1764F1533D8C.html#GUID-1F08C864-8C95-4839-BD9C-1764F1533D8C for a definition of micromirror landed duty cycle.
(13) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (for example, power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(14) The locations of thermal test points TP2, TP3, TP4, and TP5 in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477. The window test points TP2, TP3, TP4, and TP5 shown in GUID-BBB8F296-C115-47E9-9B94-CDBFBB476EDC.html#DLPS101965477 are intended to result in the worst-case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.
(16) The average over time (including storage and operating) that the device is not in the "elevated dew point temperature range."
(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
GUID-E47D1640-BD02-4BCD-9A42-A9E55B3E6BBF-low.gifFigure 6-1 Maximum Recommended DMD Temperature—Derating Curve