ZHCSOO1D December 2000 – August 2021 DCR021205 , DCR022405
PRODUCTION DATA
Each of the DCR02 series devices can be disabled or enabled by driving the SYNC pin using an open-drain CMOS gate. If the SYNC pin is pulled low, the DCR02 becomes disabled. The disable time depends upon the external loading. The internal disable function is implemented in 2 µs. Removal of the pulldown causes the DCR02 to be enabled.
Capacitive loading on the SYNC pin must be minimized (≤ 3 pF) to prevent a reduction in the oscillator frequency. The External Synchronization of the DCP01/02 Series of DC/DC Converters Application Report (SBAA035) describes disable and enable control circuitry. This document contains information on how to null the effects of additional capacitance on the SYNC pin. The oscillator’s frequency can be measured at VREC, as this is the fundamental frequency of the ripple component.