ZHCSEO3B April   2012  – January 2016 DAC101C081 , DAC101C081Q , DAC101C085

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 AC and Timing Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 DAC Section
      2. 9.3.2 Output Amplifier
      3. 9.3.3 Reference Voltage
      4. 9.3.4 Power-On Reset
      5. 9.3.5 Simultaneous Reset
      6. 9.3.6 Additional Timing Information: toutz
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
      2. 9.5.2 Basic I2C™ Protocol
      3. 9.5.3 Standard-Fast Mode
      4. 9.5.4 High-Speed (Hs) Mode
      5. 9.5.5 I2C Slave (Hardware) Address
      6. 9.5.6 Writing to the DAC Register
      7. 9.5.7 Reading from the DAC Register
    6. 9.6 Registers
      1. 9.6.1 DAC Register
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bipolar Operation
      2. 10.1.2 DSP/Microprocessor Interfacing
        1. 10.1.2.1 Interfacing to the 2-wire Bus
        2. 10.1.2.2 Interfacing to a Hs-mode Bus
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Using References as Power Supplies
      1. 11.1.1 LM4132
      2. 11.1.2 LM4050
      3. 11.1.3 LP3985
      4. 11.1.4 LP2980
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 器件命名规则
        1. 13.1.1.1 技术规格定义
    2. 13.2 相关链接
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

NGF Package
6-Pin WSON
Top View
DAC101C081 DAC101C081Q DAC101C085 30052201.gif
DDC Package
6-Lead SOT
Top View
DAC101C081 DAC101C081Q DAC101C085 30052202.gif
DGK Package
8-Lead VSSOP
Top View
DAC101C081 DAC101C081Q DAC101C085 30052210.gif

Pin Functions

PIN TYPE EQUIVALENT CIRCUIT DESCRIPTION
NAME WSON SOT VSSOP
ADR0 1 6 1 Digital Input,
three levels 		DAC101C081 DAC101C081Q DAC101C085 30052262.gif Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 and A0) of the 7-bit slave address. (see Table 1)
ADR1 — — 2 Digital Input,
three levels		 Tri-State Address Selection Input. Sets Bits A6 and A3 of the 7-bit slave address. (see Table 1)
GND 4 3 5 Ground Ground for all on-chip circuitry
PAD PAD — — Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.
SCL 2 5 3 Digital Input DAC101C081 DAC101C081Q DAC101C085 30052261.gif Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device.
SDA 3 4 4 Digital
Input/Output		 Serial Data bi-directional connection. Data is clocked into or out of the internal 16-bit register relative to the clock edges of SCL. This is an open drain data line that must be pulled to the supply (VA) by an external pullup resistor.
VA 5 2 6 Supply Power supply input. For the SOT and WSON versions, this supply is used as the reference. Must be decoupled to GND.
VOUT 6 1 8 Analog Output Analog Output Voltage
VREF — — 7 Supply Unbufferred reference voltage. For the VSSOP-8, this supply is used as the reference. VREF must be free of noise and decoupled to GND.