ZHCSUH0G August   2007  – January 2024 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 接收文档更新通知
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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9.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCEx949. All settings can be manually written to the device through the SDA/SCL bus, or are easily programmable by using the TI Pro Clock software. TI Pro Clock software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

Table 9-1 SDA/SCL Registers
ADDRESS OFFSETREGISTER DESCRIPTIONTABLE
00hGeneric configuration registerTable 9-3
10hPLL1 configuration registerTable 9-4
20hPLL2 configuration registerTable 9-5
30hPLL3 configuration registerTable 9-6
40hPLL4 configuration registerTable 9-7

The grey-highlighted Bits described in the configuration registers tables on the following pages, belong to the Control Pin Register. The user can predefine up to eight different control settings. These settings can then be selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).

Table 9-2 Configuration Register, External Control Pins
EXTERNAL CONTROL PINSY1PLL1 SETTINGPLL2 SETTINGPLL3 SETTINGPLL4 SETTING
OUTPUT SELECTFREQ SELECTSSC SELECTOUTPUT SELECTFREQ SELECTSSC SELECTOUTPUT SELECTFREQ SELECTSSC SELECTOUTPUT SELECTFREQ SELECTSSC SELECTOUTPUT SELECT
S2S1S0Y1FS1SSC1Y2Y3FS2SSC2Y4Y5FS3SSC3Y6Y7FS4SSC4Y8Y9
000Y1_0FS1_0SSC1_0Y2Y3_0FS2_0SSC2_0Y4Y5_0FS3_0SSC3_0Y6Y7_0FS4_0SSC4_0Y8Y9_0
001Y1_1FS1_1SSC1_1Y2Y3_1FS2_1SSC2_1Y4Y5_1FS3_1SSC3_1Y6Y7_1FS4_1SSC4_1Y8Y9_1
010Y1_2FS1_2SSC1_2Y2Y3_2FS2_2SSC2_2Y4Y5_2FS3_2SSC3_2Y6Y7_2FS4_2SSC4_2Y8Y9_2
011Y1_3FS1_3SSC1_3Y2Y3_3FS2_3SSC2_3Y4Y5_3FS3_3SSC3_3Y6Y7_3FS4_3SSC4_3Y8Y9_3
100Y1_4FS1_4SSC1_4Y2Y3_4FS2_4SSC2_4Y4Y5_4FS3_4SSC3_4Y6Y7_4FS4_4SSC4_4Y8Y9_4
101Y1_5FS1_5SSC1_5Y2Y3_5FS2_5SSC2_5Y4Y5_5FS3_5SSC3_5Y6Y7_5FS4_5SSC4_5Y8Y9_5
110Y1_6FS1_6SSC1_6Y2Y3_6FS2_6SSC2_6Y4Y5_6FS3_6SSC3_6Y6Y7_6FS4_6SSC4_6Y8Y9_6
111Y1_7FS1_7SSC1_7Y2Y3_7FS2_7SSC2_7Y4Y5_7FS3_7SSC3_7Y6Y7_7FS4_7SSC4_7Y8Y9_7
Addr. Offset(1)04h13h10h-12h15h23h20h-22h25h33h30h-32h35h43h40h-42h45h
(1) Address Offset refers to the byte address in the Configuration Register on following pages.
Table 9-3 Generic Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
00h7E_ELxbDevice Identification (read only): ‘1’ is CDCE949 (3.3V), ‘0’ is CDCEL949 (1.8V)
6:4RIDXbRevision Identification Number (read only)
3:0VID1hVendor Identification Number (read only)
01h7–0bReserved - always write 0
6EEPIP0bEEPROM Programming Status(4): (read only)0 – EEPROM programming is completed
1 – EEPROM is in programming mode
5EELOCK0bPermanently Lock EEPROM Data(5):0 – EEPROM is not locked
1 – EEPROM is permanently locked
4PWDN0bDevice power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
0 – device active (all PLLs and all outputs are enabled)
1 – device power down (all PLLs in power down and all outputs in 3-State)
3:2INCLK00bInput clock selection:00 – X-tal
01 – VCXO		10 – LVCMOS
11 – reserved
1:0TARGET_ADR00bProgrammable Address Bits A0 and A1 of the Target Receiver Address
02h7M11bClock source selection for output Y1:0 – input clock
1 – PLL1 clock
6SPICON0bOperation mode selection for pin 22/23(6)
0 – serial programming interface SDA (pin 23) and SCL (pin 22)
1 – control pins S1 (pin 23) and S2 (pin 22)
5:4Y1_ST111bY1-State0/1 Definition (applies to Y1_ST1 and Y1_ST0)
3:2Y1_ST001b00 – device power down (all PLLs in power down and all outputs in 3-state)
01 – Y1 disabled to 3-state
10 – Y1 disabled to low
11 – Y1 enabled (normal operation)
1:0Pdiv1 [9:8]001h10-Bit Y1-Output-Divider Pdiv1:0 – divider reset and stand-by
1-to-1023 – divider value
03h7:0Pdiv1 [7:0]
04h7Y1_70bY1_x State Selection(7)
6Y1_60b0 – State0 (predefined by Y1-State0 Definition [Y1_ST0])
1 – State1 (predefined by Y1-State1 Definition [Y1_ST1])
5Y1_50b
4Y1_40b
3Y1_30b
2Y1_20b
1Y1_11b
0Y1_00b
05h7:3XCSEL0AhCrystal load capacitor selection(8):00h → 0 pF
01h → 1 pF
02h → 2 pF
14h-to-1Fh → 20 pF		GUID-20222596-7E89-4551-B689-F472AF2310D8-low.gif
2:0—0bReserved - do not write others than 0
06h7:1BCOUNT50h7-Bit Byte Count (Defines the number of Bytes which is sent from this device at the next Block Read transfer; all bytes must be read out to correctly finish the read cycle.)
0EEWRITE0bInitiate EEPROM Write Cycle(4)(9)
0 – no EEPROM write cycle
1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
07h-0Fh——0hReserved – do not write others than 0
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless custom setting is used.
(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is completed. Data, however, can be read during the programming sequence (Byte Read or Block Read).
(5) If this bit is set high in the EEPROM, the actual data in the EEPROM is permanently locked, and no further programming is possible. Data, however can still be written through the SDA/SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM
(6) Selection of control-pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two target receiver address bits are reset to A0 = 0 and A1 = 0.
(7) These are the bits of the Control Pin Register. The user can predefine up to eight different control settings. These settings can then be selected by the external control pins, S0, S1, and S2.
(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors must be used only to do a fine adjustment of CL by few pF. The value of CL can be programmed with a resolution of 1 pF for a total crystal load range of 0 pF to 20 pF. For CL > 20 pF use additional external capacitors. Also, the device input capacitance must be considered; this adds 1.5 pF (6 pF, 2 pF) to the selected CL. For more information about VCXO configuration and crystal recommendations, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).
(9) NOTE: The EEPROM WRITE bit must be sent last to make sure the contents of all internal registers are written into the EEPROM. The EEWRITE cycle is initiated by the rising edge of the EEWRITE-Bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE-Bit must be reset low after the programming is completed. The programming status can be monitored by readout EEPIP. If EELOCK is set high, no EEPROM programming is possible.
Table 9-4 PLL1 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
10h7:5SSC1_7 [2:0]000bSSC1: PLL1 SSC Selection (Modulation Amount)(4)
4:2SSC1_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC1_5 [2:1]000b
11h7SSC1_5 [0]
6:4SSC1_4 [2:0]000b
3:1SSC1_3 [2:0]000b
0SSC1_2 [2]000b
12h7:6SSC1_2 [1:0]
5:3SSC1_1 [2:0]000b
2:0SSC1_0 [2:0]000b
13h7FS1_70bFS1_x: PLL1 Frequency Selection(4)
6FS1_60b0 – fVCO1_0 (predefined by PLL1_0 – Multiplier/Divider value)
1 – fVCO1_1 (predefined by PLL1_1 – Multiplier/Divider value)
5FS1_50b
4FS1_40b
3FS1_30b
2FS1_20b
1FS1_10b
0FS1_00b
14h7MUX11bPLL1 Multiplexer:0 – PLL1
1 – PLL1 Bypass (PLL1 is in power down)
6M21bOutput Y2 Multiplexer:0 – Pdiv1
1 – Pdiv2
5:4M310bOutput Y3 Multiplexer:00 – Pdiv1-Divider
01 – Pdiv2-Divider
10 – Pdiv3-Divider
11 – reserved
3:2Y2Y3_ST111bY2, Y3-State0/1definition:00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State (PLL1 on)
10–Y2/Y3 disabled to low (PLL1 on)
11 – Y2/Y3 enabled (normal operation, PLL1 on)
1:0Y2Y3_ST001b
15h7Y2Y3_70bY2Y3_x Output State Selection(4)
6Y2Y3_60b0 – state0 (predefined by Y2Y3_ST0)
1 – state1 (predefined by Y2Y3_ST1)
5Y2Y3_50b
4Y2Y3_40b
3Y2Y3_30b
2Y2Y3_20b
1Y2Y3_11b
0Y2Y3_00b
16h7SSC1DC0bPLL1 SSC down/center selection:0 – down
1 – center
6:0Pdiv201h7-Bit Y2-Output-Divider Pdiv2:0 – reset and stand-by
1-to-127 – divider value
17h7—0bReserved – do not write others than 0
6:0Pdiv301h7-Bit Y3-Output-Divider Pdiv3:0 – reset and stand-by
1-to-127 – divider value
18h7:0PLL1_0N [11:4004hPLL1_0(5): 30-Bit Multiplier/Divider value for frequency fVCO1_0
(for more information, see PLL Frequency Planning)
19h7:4PLL1_0N [3:0]
3:0PLL1_0R [8:5]000h
1Ah7:3PLL1_0R[4:0]
2:0PLL1_0Q [5:3]10h
1Bh7:5PLL1_0Q [2:0]
4:2PLL1_0P [2:0]010b
1:0VCO1_0_RANGE00bfVCO1_0 range selection:00 – fVCO1_0 < 125 MHz
01 – 125 MHz ≤ fVCO1_0 < 150 MHz
10 – 150 MHz ≤ fVCO1_0 < 175 MHz
11 – fVCO1_0 ≥ 175 MHz
1Ch7:0PLL1_1N [11:4]004hPLL1_1(5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
1Dh7:4PLL1_1N [3:0]
3:0PLL1_1R [8:5]000h
1Eh7:3PLL1_1R[4:0]
2:0PLL1_1Q [5:3]10h
1Fh7:5PLL1_1Q [2:0]
4:2PLL1_1P [2:0]010b
1:0VCO1_1_RANGE00bfVCO1_1 range selection:00 – fVCO1_1 < 125 MHz
01 – 125 MHz ≤ fVCO1_1 < 150 MHz
10 – 150 MHz ≤ fVCO1_1 < 175 MHz
11 – fVCO1_1 ≥ 175 MHz
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Table 9-5 PLL2 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
20h7:5SSC2_7 [2:0]000bSSC2: PLL2 SSC Selection (Modulation Amount)(4)
4:2SSC2_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC2_5 [2:1]000b
21h7SSC2_5 [0]
6:4SSC2_4 [2:0]000b
3:1SSC2_3 [2:0]000b
0SSC2_2 [2]000b
22h7:6SSC2_2 [1:0]
5:3SSC2_1 [2:0]000b
2:0SSC2_0 [2:0]000b
23h7FS2_70bFS2_x: PLL2 Frequency Selection(4)
6FS2_60b0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5FS2_50b
4FS2_40b
3FS2_30b
2FS2_20b
1FS2_10b
0FS2_00b
24h7MUX21bPLL2 Multiplexer:0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
6M41bOutput Y4 Multiplexer:0 – Pdiv2
1 – Pdiv4
5:4M510bOutput Y5 Multiplexer:00 – Pdiv2-Divider
01 – Pdiv4-Divider
10 – Pdiv5-Divider
11 – reserved
3:2Y4Y5_ST111bY4, Y5-State0/1definition:00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
11 – Y4/Y5 enabled (normal operation, PLL2 on)
1:0Y4Y5_ST001b
25h7Y4Y5_70bY4Y5_x Output State Selection(4)
6Y4Y5_60b0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
5Y4Y5_50b
4Y4Y5_40b
3Y4Y5_30b
2Y4Y5_20b
1Y4Y5_11b
0Y4Y5_00b
26h7SSC2DC0bPLL2 SSC down/center selection:0 – down
1 – center
6:0Pdiv401h7-Bit Y4-Output-Divider Pdiv4:0 – reset and stand-by
1-to-127 – divider value
27h7—0bReserved – do not write others than 0
6:0Pdiv501h7-Bit Y5-Output-Divider Pdiv5:0 – reset and stand-by
1-to-127 – divider value
28h7:0PLL2_0N [11:4004hPLL2_0(5): 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information, see PLL Frequency Planning).
29h7:4PLL2_0N [3:0]
3:0PLL2_0R [8:5]000h
2Ah7:3PLL2_0R[4:0]
2:0PLL2_0Q [5:3]10h
2Bh7:5PLL2_0Q [2:0]
4:2PLL2_0P [2:0]010b
1:0VCO2_0_RANGE00bfVCO2_0 range selection:00 – fVCO2_0 < 125 MHz
01 – 125 MHz ≤ fVCO2_0 < 150 MHz
10 – 150 MHz ≤ fVCO2_0 < 175 MHz
11 – fVCO2_0 ≥ 175 MHz
2Ch7:0PLL2_1N [11:4]004hPLL2_1(5): 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information, see PLL Frequency Planning).
2Dh7:4PLL2_1N [3:0]
3:0PLL2_1R [8:5]000h
2Eh7:3PLL2_1R[4:0]
2:0PLL2_1Q [5:3]10h
2Fh7:5PLL2_1Q [2:0]
4:2PLL2_1P [2:0]010b
1:0VCO2_1_RANGE00bfVCO2_1 range selection:00 – fVCO2_1 < 125 MHz
01 – 125 MHz ≤ fVCO2_1 < 150 MHz
10 – 150 MHz ≤ fVCO2_1 < 175 MHz
11 – fVCO2_1 ≥ 175 MHz
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Table 9-6 PLL3 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
30h7:5SSC3_7 [2:0]000bSSC3: PLL3 SSC Selection (Modulation Amount)(4)
4:2SSC3_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC3_5 [2:1]000b
31h7SSC3_5 [0]
6:4SSC3_4 [2:0]000b
3:1SSC3_3 [2:0]000b
0SSC3_2 [2]000b
32h7:6SSC3_2 [1:0]
5:3SSC3_1 [2:0]000b
2:0SSC3_0 [2:0]000b
33h7FS3_70bFS3_x: PLL3 Frequency Selection(4)
6FS3_60b0 – fVCO3_0 (predefined by PLL3_0 – Multiplier/Divider value)
1 – fVCO3_1 (predefined by PLL3_1 – Multiplier/Divider value)
5FS3_50b
4FS3_40b
3FS3_30b
2FS3_20b
1FS3_10b
0FS3_00b
34h7MUX31bPLL3 Multiplexer:0 – PLL3
1 – PLL3 Bypass (PLL3 is in power down)
6M61bOutput Y6 Multiplexer:0 – Pdiv4
1 – Pdiv6
5:4M710bOutput Y7 Multiplexer:00 – Pdiv4-Divider
01 – Pdiv6-Divider
10 – Pdiv7-Divider
11 – reserved
3:2Y6Y7_ST111bY6, Y7-State0/1definition:00 – Y6/Y7 disabled to 3-State (PLL3 is in power down)
01 – Y6/Y7 disabled to 3-State (PLL3 on)
10 –Y6/Y7 disabled to low (PLL3 on)
11 – Y6/Y7 enabled (normal operation, PLL3 on)
1:0Y6Y7_ST001b
35h7Y6Y7_70bY6Y7_x Output State Selection(4)
6Y6Y7_60b0 – state0 (predefined by Y6Y7_ST0)
1 – state1 (predefined by Y6Y7_ST1)
5Y6Y7_50b
4Y6Y7_40b
3Y6Y7_30b
2Y6Y7_20b
1Y6Y7_11b
0Y6Y7_00b
36h7SSC3DC0bPLL3 SSC down/center selection:0 – down
1 – center
6:0Pdiv601h7-Bit Y6-Output-Divider Pdiv6:0 – reset and stand-by
1-to-127 – divider value
37h7—0bReserved – do not write others than 0
6:0Pdiv701h7-Bit Y7-Output-Divider Pdiv7:0 – reset and stand-by
1-to-127 – divider value
38h7:0PLL3_0N [11:4004hPLL3_0(5): 30-Bit Multiplier/Divider value for frequency fVCO3_0
(for more information, see PLL Frequency Planning).
39h7:4PLL3_0N [3:0]
3:0PLL3_0R [8:5]000h
3Ah7:3PLL3_0R[4:0]
2:0PLL3_0Q [5:3]10h
3Bh7:5PLL3_0Q [2:0]
4:2PLL3_0P [2:0]010b
1:0VCO3_0_RANGE00bfVCO3_0 range selection:00 – fVCO3_0 < 125 MHz
01 – 125 MHz ≤ fVCO3_0 < 150 MHz
10 – 150 MHz ≤ fVCO3_0 < 175 MHz
11 – fVCO3_0 ≥ 175 MHz
3Ch7:0PLL3_1N [11:4]004hPLL3_1(5): 30-Bit Multiplier/Divider value for frequency fVCO3_1
(for more information, see PLL Frequency Planning).
3Dh7:4PLL3_1N [3:0]
3:0PLL3_1R [8:5]000h
3Eh7:3PLL3_1R[4:0]
2:0PLL3_1Q [5:3]10h
3Fh7:5PLL3_1Q [2:0]
4:2PLL3_1P [2:0]010b
1:0VCO3_1_RANGE00bfVCO3_1 range selection:00 – fVCO3_1 < 125 MHz
01 – 125 MHz ≤ fVCO3_1 < 150 MHz
10 – 150 MHz ≤ fVCO3_1 < 175 MHz
11 – fVCO3_1 ≥ 175 MHz
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
Table 9-7 PLL4 Configuration Register
OFFSET(1)BIT(2)ACRONYMDEFAULT(3)DESCRIPTION
40h7:5SSC4_7 [2:0]000bSSC4: PLL4 SSC Selection (Modulation Amount)(4)
4:2SSC4_6 [2:0]000bDown
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0SSC4_5 [2:1]000b
41h7SSC4_5 [0]
6:4SSC4_4 [2:0]000b
3:1SSC4_3 [2:0]000b
0SSC4_2 [2]000b
42h7:6SSC4_2 [1:0]
5:3SSC4_1 [2:0]000b
2:0SSC4_0 [2:0]000b
43h7FS4_70bFS4_x: PLL4 Frequency Selection(4)sl
6FS4_60b0 – fVCO4_0 (predefined by PLL4_0 – Multiplier/Divider value)
1 – fVCO4_1 (predefined by PLL4_1 – Multiplier/Divider value)
5FS4_50b
4FS4_40b
3FS4_30b
2FS4_20b
1FS4_10b
0FS4_00b
44h7MUX41bPLL4 Multiplexer:0 – PLL4
1 – PLL4 Bypass (PLL4 is in power down)
6M81bOutput Y8 Multiplexer:0 – Pdiv6
1 – Pdiv8
5:4M910bOutput Y9 Multiplexer:00 – Pdiv6-Divider
01 – Pdiv8-Divider
10 – Pdiv9-Divider
11 – reserved
3:2Y8Y9_ST111bY8, Y9-State0/1definition:00 – Y8/Y9 disabled to 3-State (PLL4 is in power down)
01 – Y8/Y9 disabled to 3-State (PLL4 on)
10 –Y8/Y9 disabled to low (PLL4 on)
11 – Y8/Y9 enabled (normal operation, PLL4 on)
1:0Y8Y9_ST001b
45h7Y8Y9_70bY8Y9_x Output State Selection(4)
6Y8Y9_60b0 – state0 (predefined by Y8Y9_ST0)
1 – state1 (predefined by Y8Y9_ST1)
5Y8Y9_50b
4Y8Y9_40b
3Y8Y9_30b
2Y8Y9_20b
1Y8Y9_11b
0Y8Y9_00b
46h7SSC4DC0bPLL4 SSC down/center selection:0 – down
1 – center
6:0Pdiv801h7-Bit Y8-Output-Divider Pdiv8:0 – reset and stand-by
1-to-127 – divider value
47h7—0bReserved – do not write others than 0
6:0Pdiv901h7-Bit Y9-Output-Divider Pdiv9:0 – reset and stand-by
1-to-127 – divider value
48h7:0PLL4_0N [11:4004hPLL4_0(5): 30-Bit Multiplier/Divider value for frequency fVCO4_0
(for more information, see PLL Frequency Planning).
49h7:4PLL4_0N [3:0]
3:0PLL4_0R [8:5]000h
4Ah7:3PLL4_0R[4:0]
2:0PLL4_0Q [5:3]10h
4Bh7:5PLL4_0Q [2:0]
4:2PLL4_0P [2:0]010b
1:0VCO4_0_RANGE00bfVCO4_0 range selection:00 – fVCO4_0 < 125 MHz
01 – 125 MHz ≤ fVCO4_0 < 150 MHz
10 – 150 MHz ≤ fVCO4_0 < 175 MHz
11 – fVCO4_0 ≥ 175 MHz
4Ch7:0PLL4_1N [11:4]004hPLL4_1(5): 30-Bit Multiplier/Divider value for frequency fVCO4_1
(for more information, see PLL Frequency Planning).
4Dh7:4PLL4_1N [3:0]
3:0PLL4_1R [8:5]000h
4Eh7:3PLL4_1R[4:0]
2:0PLL4_1Q [5:3]10h
4Fh7:5PLL4_1Q [2:0]
4:2PLL4_1P [2:0]010b
1:0VCO4_1_RANGE00bfVCO4_1 range selection:00 – fVCO4_1 < 125 MHz
01 – 125 MHz ≤ fVCO4_1 < 150 MHz
10 – 150 MHz ≤ fVCO4_1 < 175 MHz
11 – fVCO4_1 ≥ 175 MHz
(1) Writing data beyond 50h may adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.
(5) PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤7, 0 ≤ r ≤ 511, 0 < N < 4096