ZHCSLN5D december   2010  – september 2020 BQ24133

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
    1.     Pin Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Battery Voltage Regulation
      2. 9.3.2  Battery Current Regulation
      3. 9.3.3  Battery Precharge Current Regulation
      4. 9.3.4  Input Current Regulation
      5. 9.3.5  Charge Termination, Recharge, And Safety Timers
      6. 9.3.6  Power Up
      7. 9.3.7  Input Undervoltage Lockout (UVLO)
      8. 9.3.8  Input Overvoltage/Undervoltage Protection
      9. 9.3.9  Enable and Disable Charging
      10. 9.3.10 System Power Selector
      11. 9.3.11 Converter Operation
      12. 9.3.12 Automatic Internal Soft-Start Charger Current
      13. 9.3.13 Charge Overcurrent Protection
      14. 9.3.14 Charge Undercurrent Protection
      15. 9.3.15 Battery Detection
        1. 9.3.15.1 Example
      16. 9.3.16 Battery Short Protection
      17. 9.3.17 Battery Overvoltage Protection
      18. 9.3.18 Temperature Qualification
      19. 9.3.19 MOSFET Short Circuit and Inductor Short Circuit Protection
      20. 9.3.20 Thermal Regulation and Shutdown Protection
      21. 9.3.21 Timer Fault Recovery
      22. 9.3.22 Charge Status Outputs
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
        4. 10.2.2.4 Input Filter Design
        5. 10.2.2.5 Input ACFET and RBFET Selection
        6. 10.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Functions

PINTYPEDESCRIPTION
NAMENO.
ACDRV8OAC adapter to system switch driver output. Connect to 4-kΩ resistor then to the gate of the ACFET N-channel power MOSFET and the reverse conduction blocking N-channel power MOSFET. Connect both FETs as common-source. The internal gate drive is asymmetrical, allowing a quick turnoff and slower turnon in addition to the internal break-before-make logic with respect to the BATDRV.
ACN5IAdapter current sense resistor negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND for common-mode filtering.
ACP6P/IAdapter current sense resistor positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.
ACSET17IInput current set point. Use a voltage divider from VREF to ACSET to AGND to set this value:
GUID-0D09D5F3-5496-4839-A9B4-43056F6E7F36-low.gif
AGNDThermal PadPExposed pad beneath the IC. Always solder Thermal Pad to the board, and have vias on the Thermal Pad plane star-connecting to AGND and ground plane for high-current power converter. It dissipates the heat from the IC.
AVCC4PIC power positive supply. Place a 1-µF ceramic capacitor from AVCC to AGND and place it as close as possible to IC. Place a 10-Ω resistor from input side to AVCC pin to filter the noise. For 5-V input, a 5-Ω resistor is recommended.
BATDRV19OBattery discharge MOSFET gate driver output. Connect to 1-kΩ resistor to the gate of the BATFET P-channel power MOSFET. Connect the source of the BATFET to the system load voltage node. Connect the drain of the BATFET to the battery pack positive node. The internal gate drive is asymmetrical to allow a quick turnoff and slower turnon, in addition to the internal break-before-make logic with respect to ACDRV.
BTST21PPWM high-side driver positive supply. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
CELL14ICell selection pin. Set CELL pin LOW for 1-cell, Float for 2-cell (0.8 V - 1.8 V), and HIGH for 3-cell with a fixed 4.2 V per cell.
CMSRC7OConnect to common source of N-channel ACFET and reverse blocking MOSFET (RBFET). Place 4-kΩ resistor from CMSRC pin to the common source of ACFET and RBFET to control the turnon speed. The resistance between ACDRV and CMSRC should be 500 kΩ or bigger.
ISET13IFast charge current set point. Use a voltage divider from VREF to ISET to AGND to set the fast charge current:
GUID-B1CE41DE-EA43-4722-9424-7DB8A856B9A2-low.gif
The precharge and termination current is internally as one tenth of the charge current. The charger is disabled when ISET pin voltage is below 40 mV and enabled when ISET pin voltage is above 120 mV.
OVPSET18IValid input voltage set point. Use a voltage divider from input to OVPSET to AGND to set this voltage. The voltage above internal 1.6-V reference indicates input overvoltage, and the voltage below internal 0.5-V reference indicates input undervoltage. In either condition, charge terminates, and input NMOS pair ACFET/RBFET turn off. LED driven by STAT pin keeps blinking, reporting fault condition.
PGND22, 23PPower ground. Ground connection for high-current power converter node. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. Only connect to AGND through the Thermal Pad underneath the IC.
PVCC2, 3PCharger input voltage. Connect at least 10-µF ceramic capacitor from PVCC to PGND and place it as close as possible to IC.
REGN 20PPWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to PGND pin, close to the IC. Generate high-side driver bootstrap voltage by integrated diode from REGN to BTST.
SRN15ICharge current sense resistor negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRN pin to AGND for common-mode filtering.
SRP16I/PCharge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.
STAT9OOpen-drain charge status pin with 10-kΩ pullup to power rail. The STAT pin can be used to drive LED or communicate with the host processor. It indicates various charger operations: LOW when charge in progress. HIGH when charge is complete or in SLEEP mode. Blinking at 0.5 Hz when fault occurs, including charge suspend, input overvoltage, timer fault and battery absent.
SW1, 24PSwitching node, charge current output inductor connection. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
TS10ITemperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to AGND. The temperature qualification window can be set to 5-40°C or wider. The 103AT thermistor is recommended.
TTC11ISafety Timer and termination control. Connect a capacitor from this node to AGND to set the fast charge safety timer(5.6 min/nF). Precharge timer is internally fixed to 30 minutes. Pull the TTC to LOW to disable the charge termination and safety timer. Pull the TTC to HIGH to disable the safety timer but allow the charge termination.
VREF12P3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to AGND pin close to the IC. This voltage could be used for programming ISET and ACSET and TS pins. It may also serve as the pullup rail of STAT pin and CELL pin.