SBAS860 August   2017 ADC31RF80

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance Characteristics: fS = 2949.12 MSPS
    7. 6.7  AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A + D Band)
    8. 6.8  AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A Band)
    9. 6.9  Digital Requirements
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Input Clock Diagram
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
        1. 8.3.1.1 Input Clamp Circuit
      2. 8.3.2  Clock Input
      3. 8.3.3  SYSREF Input
        1. 8.3.3.1 Using SYSREF
        2. 8.3.3.2 Frequency of the SYSREF Signal
      4. 8.3.4  DDC Block
        1. 8.3.4.1 Operating Mode: Receiver
        2. 8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
        3. 8.3.4.3 Decimation Filters
          1. 8.3.4.3.1  Divide-by-4
          2. 8.3.4.3.2  Divide-by-6
          3. 8.3.4.3.3  Divide-by-8
          4. 8.3.4.3.4  Divide-by-9
          5. 8.3.4.3.5  Divide-by-10
          6. 8.3.4.3.6  Divide-by-12
          7. 8.3.4.3.7  Divide-by-16
          8. 8.3.4.3.8  Divide-by-18
          9. 8.3.4.3.9  Divide-by-20
          10. 8.3.4.3.10 Divide-by-24
          11. 8.3.4.3.11 Divide-by-32
          12. 8.3.4.3.12 Latency With Decimation Options
        4. 8.3.4.4 Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 8.3.5  NCO Switching
      6. 8.3.6  SerDes Transmitter Interface
      7. 8.3.7  Eye Diagrams
      8. 8.3.8  Alarm Outputs: Power Detectors for AGC Support
        1. 8.3.8.1 Absolute Peak Power Detector
        2. 8.3.8.2 Crossing Detector
        3. 8.3.8.3 RMS Power Detector
        4. 8.3.8.4 GPIO AGC MUX
      9. 8.3.9  Power-Down Mode
      10. 8.3.10 ADC Test Pattern
        1. 8.3.10.1 Digital Block
        2. 8.3.10.2 Transport Layer
        3. 8.3.10.3 Link Layer
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Frame Assembly
        3. 8.4.2.3 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        4. 8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 8.4.2.6 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        7. 8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 8.4.3 Serial Interface
        1. 8.4.3.1 Serial Register Write: Analog Bank
        2. 8.4.3.2 Serial Register Readout: Analog Bank
        3. 8.4.3.3 Serial Register Write: Digital Bank
        4. 8.4.3.4 Serial Register Readout: Digital Bank
        5. 8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
    5. 8.5 Register Maps
      1. 8.5.1  Example Register Writes
      2. 8.5.2  Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 000h (address = 000h), General Registers
          2. 8.5.2.1.2 Register 002h (address = 002h), General Registers
          3. 8.5.2.1.3 Register 003h (address = 003h), General Registers
          4. 8.5.2.1.4 Register 004h (address = 004h), General Registers
          5. 8.5.2.1.5 Register 010h (address = 010h), General Registers
          6. 8.5.2.1.6 Register 011h (address = 011h), General Registers
          7. 8.5.2.1.7 Register 012h (address = 012h), General Registers
      3. 8.5.3  Master Page (M = 0)
        1. 8.5.3.1 Register 020h (address = 020h), Master Page
        2. 8.5.3.2 Register 032h (address = 032h), Master Page
        3. 8.5.3.3 Register 039h (address = 039h), Master Page
        4. 8.5.3.4 Register 03Ch (address = 03Ch), Master Page
        5. 8.5.3.5 Register 05Ah (address = 05Ah), Master Page
        6. 8.5.3.6 Register 03Dh (address = 3Dh), Master Page
        7. 8.5.3.7 Register 057h (address = 057h), Master Page
        8. 8.5.3.8 Register 058h (address = 058h), Master Page
      4. 8.5.4  ADC Page (FFh, M = 0)
        1. 8.5.4.1 Register 03Fh (address = 03Fh), ADC Page
        2. 8.5.4.2 Register 042h (address = 042h), ADC Page
      5. 8.5.5  Digital Function Page (610000h, M = 1)
        1. 8.5.5.1 Register A6h (address = 0A6h), Digital Function Page
      6. 8.5.6  Offset Corr Page (610000h, M = 1)
        1. 8.5.6.1 Register 034h (address = 034h), Offset Corr Page
        2. 8.5.6.2 Register 068h (address = 068h), Offset Corr Page
      7. 8.5.7  Digital Gain Page (610005h, M = 1)
        1. 8.5.7.1 Register 0A6h (address = 0A6h), Digital Gain Page
      8. 8.5.8  Main Digital Page (680000h, M = 1)
        1. 8.5.8.1  Register 000h (address = 000h), Main Digital Page
        2. 8.5.8.2  Register 0A2h (address = 0A2h), Main Digital Page
        3. 8.5.8.3  Register 0A5h (address = 0A5h), Main Digital Page
        4. 8.5.8.4  Register 0A9h (address = 0A9h), Main Digital Page
        5. 8.5.8.5  Register 0B0h (address = 0B0h), Main Digital Page
        6. 8.5.8.6  Register 0B1h (address = 0B1h), Main Digital Page
        7. 8.5.8.7  Register 0B2h (address = 0B2h), Main Digital Page
        8. 8.5.8.8  Register 0B3h (address = 0B3h), Main Digital Page
        9. 8.5.8.9  Register 0B4h (address = 0B4h), Main Digital Page
        10. 8.5.8.10 Register 0B5h (address = 0B5h), Main Digital Page
        11. 8.5.8.11 Register 0B6h (address = 0B6h), Main Digital Page
        12. 8.5.8.12 Register 0B7h (address = 0B7h), Main Digital Page
        13. 8.5.8.13 Register 0B8h (address = 0B8h), Main Digital Page
        14. 8.5.8.14 Register 0B9h (address = 0B9h), Main Digital Page
        15. 8.5.8.15 Register 0BAh (address = 0BAh), Main Digital Page
        16. 8.5.8.16 Register 0BBh (address = 0BBh), Main Digital Page
      9. 8.5.9  JESD Digital Page (6900h, M = 1)
        1. 8.5.9.1  Register 001h (address = 001h), JESD Digital Page
        2. 8.5.9.2  Register 002h (address = 002h ), JESD Digital Page
        3. 8.5.9.3  Register 003h (address = 003h), JESD Digital Page
        4. 8.5.9.4  Register 004h (address = 004h), JESD Digital Page
        5. 8.5.9.5  Register 006h (address = 006h), JESD Digital Page
        6. 8.5.9.6  Register 007h (address = 007h), JESD Digital Page
        7. 8.5.9.7  Register 016h (address = 016h), JESD Digital Page
        8. 8.5.9.8  Register 017h (address = 017h), JESD Digital Page
        9. 8.5.9.9  Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 8.5.9.10 Register 036h (address = 036h), JESD Digital Page
        11. 8.5.9.11 Register 037h (address = 037h), JESD Digital Page
        12. 8.5.9.12 Register 03Ch (address = 03Ch), JESD Digital Page
        13. 8.5.9.13 Register 03Eh (address = 03Eh), JESD Digital Page
      10. 8.5.10 Decimation Filter Page
        1. 8.5.10.1  Register 000h (address = 000h), Decimation Filter Page
        2. 8.5.10.2  Register 001h (address = 001h), Decimation Filter Page
        3. 8.5.10.3  Register 002h (address = 2h), Decimation Filter Page
        4. 8.5.10.4  Register 005h (address = 005h), Decimation Filter Page
        5. 8.5.10.5  Register 007h (address = 007h), Decimation Filter Page
        6. 8.5.10.6  Register 008h (address = 008h), Decimation Filter Page
        7. 8.5.10.7  Register 009h (address = 009h), Decimation Filter Page
        8. 8.5.10.8  Register 00Ah (address = 00Ah), Decimation Filter Page
        9. 8.5.10.9  Register 00Bh (address = 00Bh), Decimation Filter Page
        10. 8.5.10.10 Register 00Ch (address = 00Ch), Decimation Filter Page
        11. 8.5.10.11 Register 00Dh (address = 00Dh), Decimation Filter Page
        12. 8.5.10.12 Register 00Eh (address = 00Eh), Decimation Filter Page
        13. 8.5.10.13 Register 00Fh (address = 00Fh), Decimation Filter Page
        14. 8.5.10.14 Register 010h (address = 010h), Decimation Filter Page
        15. 8.5.10.15 Register 011h (address = 011h), Decimation Filter Page
        16. 8.5.10.16 Register 014h (address = 014h), Decimation Filter Page
        17. 8.5.10.17 Register 016h (address = 016h), Decimation Filter Page
        18. 8.5.10.18 Register 01Eh (address = 01Eh), Decimation Filter Page
        19. 8.5.10.19 Register 01Fh (address = 01Fh), Decimation Filter Page
        20. 8.5.10.20 Register 033h-036h (address = 033h-036h), Decimation Filter Page
        21. 8.5.10.21 Register 037h (address = 037h), Decimation Filter Page
        22. 8.5.10.22 Register 038h (address = 038h), Decimation Filter Page
        23. 8.5.10.23 Register 039h (address = 039h), Decimation Filter Page
        24. 8.5.10.24 Register 03Ah (address = 03Ah), Decimation Filter Page
      11. 8.5.11 Power Detector Page
        1. 8.5.11.1  Register 000h (address = 000h), Power Detector Page
        2. 8.5.11.2  Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 8.5.11.3  Register 003h (address = 003h), Power Detector Page
        4. 8.5.11.4  Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 8.5.11.5  Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 8.5.11.6  Register 00Dh (address = 00Dh), Power Detector Page
        7. 8.5.11.7  Register 00Eh (address = 00Eh), Power Detector Page
        8. 8.5.11.8  Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 8.5.11.9  Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 8.5.11.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 8.5.11.11 Register 020h (address = 020h), Power Detector Page
        12. 8.5.11.12 Register 021h (address = 021h), Power Detector Page
        13. 8.5.11.13 Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 8.5.11.14 Register 027h (address = 027h), Power Detector Page
        15. 8.5.11.15 Register 02Bh (address = 02Bh), Power Detector Page
        16. 8.5.11.16 Register 032h-035h (address = 032h-035h), Power Detector Page
        17. 8.5.11.17 Register 037h (address = 037h), Power Detector Page
        18. 8.5.11.18 Register 038h (address = 038h), Power Detector Page
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
        1. 9.1.3.1 External Clock Phase Noise Consideration
      4. 9.1.4 Power Consumption in Different Modes
      5. 9.1.5 Using DC Coupling in the ADC31RF80
        1. 9.1.5.1 Bypassing the Offset Corrector Block
          1. 9.1.5.1.1 Effect of Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Start-Up Sequence

The steps in Table 127 are recommended as the power-up sequence when the ADC31RF80 is in the decimation-by-4 complex output mode.

Table 127. Initialization Sequence

STEP DESCRIPTION PAGE, REGISTER ADDRESS AND DATA COMMENT
1 Supply all supply voltages. There is no required power-supply sequence for the 1.15 V, 1.2 V, and 1.9 V supplies, and can be supplied in any order.
2 Provide the SYSREF signal.
3 Pulse a hardware reset (low-to-high-to-low) on pins 33 and 34.
4 Write the register addresses described in the PowerUpConfig file. See the files located in SBAA226 The Power-up config file contains analog trim registers that are required for best performance of the ADC. Write these registers every time after power up.
5 Write the register addresses mentioned in the ILConfigNyqX file, where X is the Nyquist zone. See the files located in SBAA226 Based on the signal band of interest, provide the Nyquist zone information to the device.
6.1 Wait for 50 ms for the device to estimate the interleaving errors.
7 Depending upon the Nyquist band of operation, choose and write the registers from the appropriate file, NLConfigNyqX, where X is the Nyquist zone. See the files located in SBAA226 Third-order nonlinearity of the device is optimized by this step for channel A.
8 Configure the JESD interface and DDC block by writing the registers mentioned in the DDC Config file. See the files located in SBAA226 Determine the DDC and JESD interface LMFS options. Program these options in this step.

Hardware Reset

Figure 262 and Table 128 provide the timing information for the hardware reset.

ADC31RF80 hardware_reset_sbas747.gif Figure 262. Hardware Reset Timing Diagram

Table 128. Hardware Reset Timing Information

MIN TYP MAX UNIT
t1 Power-on delay from power-up to active high RESET pulse 1 ms
t2 Reset pulse duration: active high RESET pulse duration 1 µs
t3 Register write delay from RESET disable to SEN active 100 ns

SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 5: quantization noise, thermal noise, and jitter. The quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

Equation 5. ADC31RF80 snr_adc_eq_sbas747.gif

Equation 6 calculates the SNR limitation resulting from sample clock jitter:

Equation 6. ADC31RF80 snr_jitter_eq_sbas747.gif

The total clock jitter (TJitter) has two components: the internal aperture jitter (90 fS) is set by the noise of the clock input buffer and the external clock jitter. Equation 7 calculates TJitter:

Equation 7. ADC31RF80 total_clck_jitter_sbas747.gif

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADC31RF80 has a thermal noise of approximately 63 dBFS and an internal aperture jitter of 90 fS. Figure 263 shows the SNR in relation to the amount of external jitter for different input frequencies.

ADC31RF80 D048_ADC32RF45.gif Figure 263. ADC SNR vs Input Frequency and External Clock Jitter

External Clock Phase Noise Consideration

As shown in Figure 264, external clock jitter can be calculated by integrating the phase noise of the clock source out to approximately two times of the ADC sampling rate (2 × fS), . In order to maximize the ADC SNR, an external band-pass filter is recommended to be used on the clock input. This filter reduces the jitter contribution from the broadband clock phase noise floor by effectively reducing the integration bandwidth to the pass band of the band-pass filter. This method is suitable when estimating the overall ADC SNR resulting from clock jitter at a certain input frequency.

ADC31RF80 adc_snr_sbas747.gif Figure 264. Integration Bandwidth for Extracting Jitter From Clock Phase Noise

However, when estimating the affect of a nearby blocker (such as a strong in-band interferer to the sensitivity), as shown in Figure 265, the phase noise information can be used directly to estimate the noise budget contribution at a certain offset frequency.

ADC31RF80 phase_noise_info_sbas747.gif Figure 265. Small Wanted Signal in Presence of Interferer

At the sampling instant, the phase noise profile of the clock source convolves with the input signal (for example, the small wanted signal and the strong interferer merge together). If the power of the clock phase noise in the signal band of interest is too large, the wanted signal cannot not be recovered.

The resulting equivalent phase noise at the ADC input is also dependent on the sampling rate of the ADC and frequency of the input signal. Equation 8 shows how the ADC sampling rate scales the clock phase noise.

Equation 8. ADC31RF80 adc_nsd_eq_sbas747.gif

Using this information, the noise contribution resulting from the phase noise profile of the ADC sampling clock can be calculated.

Power Consumption in Different Modes

The ADC31RF80 consumes approximately 4 W with a divide-by-4 complex output. When different DDC options are used, the power consumption on the DVDD supply changes by a small amount but remains unaffected on other supplies.

Table 129 and Table 130 show power consumption in different DDC modes.

Table 129. Power Consumption in Different DDC Modes (Sampling Clock Frequency, fS = 2457.6 MSPS)

DECIMATION OPTION ACTIVE DDC AVDD1P9 (mA) AVDD1P2 (mA) DVDD1P2 (mA) TOTAL POWER (mW)
Divide-by-4 Single 914 447 817 3190
Divide-by-8 Dual 913 449 890 3275
Divide-by-8 Single 914 449 789 3160
Divide-by-16 Dual 914 450 880 3266
Divide-by-16 Single 914 449 777 3147
Divide-by-24 Dual 911 450 864 3242
Divide-by-24 Single 911 449 747 3106
Divide-by-32 Dual 910 450 810 3178
Divide-by-32 Single 910 449 710 3062

Table 130. Power Consumption in Different DDC Modes (Sampling Clock Frequency, fS = 2949.12 MSPS)

DECIMATION OPTION ACTIVE DDC AVDD1P9 (mA) AVDD1P2 (mA) DVDD1P2 (mA) TOTAL POWER (mW)
Divide-by-4 Single 956 499 975 3512
Divide-by-8 Dual 957 500 1060 3612
Divide-by-8 Single 957 500 945 3480
Divide-by-16 Dual 958 525 1061 3644
Divide-by-16 Single 958 524 938 3502
Divide-by-24 Dual 955 524 1027 3598
Divide-by-24 Single 955 523 904 3456
Divide-by-32 Dual 954 523 976 3536
Divide-by-32 Single 954 522 860 3402

Using DC Coupling in the ADC31RF80

The ADC31RF80 can be used in dc-coupling applications. However, the following points must be considered when designing the system:

  1. Ensure that the correct common-mode voltage is used at the ADC analog inputs.
  2. The analog inputs are internally self-biased to VCM through approximately a 33-Ω resistor. The internal biasing resistors also function as a termination resistor. However, if a different termination is required, as shown in Figure 266, the external resistor RTERM can be differentially placed between the analog inputs. The amplifier VOCM pin is recommended to be driven from the CM pin of the ADC to help the amplifier output common-mode voltage track the required common-mode voltage of the ADC.

    ADC31RF80 dc_coupling_app_sbas860.gif
    Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω.
    RDC is approximately 65 Ω.
    Figure 266. The ADC31RF80 in a DC-Coupling Application
  3. Ensure that the correct SPI settings are written to the ADC.
  4. As shown in Figure 267, the ADC31RF80 has a digital block that estimates and corrects the offset mismatch among four interleaving ADC cores.

    ADC31RF80 offset_corr_lck_sbas747.gif Figure 267. Offset Corrector in the ADC31RF80

    The offset corrector block nullifies dc, fS / 8, fS / 4, 3 fS / 8, and fS / 2. The resulting spectrum becomes free from static spurs at these frequencies. The corrector continuously processes the data coming from the interleaving ADC cores and cannot distinguish if the tone at these frequencies is part of signal or if the tone originated from a mismatch among the interleaving ADC cores. Thus, in applications where the signal is present at these frequencies, the offset corrector block can be bypassed.

Bypassing the Offset Corrector Block

When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector is frozen so that the last estimated value is held. Required register writes are provided in Table 131.

Table 131. Freezing and Bypassing the Offset Corrector Block

STEP REGISTER WRITE COMMENT
STEPS FOR FREEZING THE CORRECTOR BLOCK
1 Signal source is turned off. The device detects an idle channel at its input.
2 Wait for at least 0.4 ms for the corrector to estimate the internal offset
3 Address 4001h, value 00h Select the offset corr page
Address 4002h, value 00h
Address 4003h, value 00h
Address 4004h, value 61h
Address 6068h, value C2h Freeze the corrector
4 Signal source can now be turned on
STEPS FOR BYPASSING THE CORRECTOR BLOCK
1 Address 4001h, value 00h
Address 4002h, value 00h
Address 4003h, value 00h
Address 4004h, value 61h Select the offset corr page
Address 6068h, value 46h Disable the corrector

Effect of Temperature

Figure 268 and Figure 269 show the behavior of nfS / 8 tones with respect to temperature when the offset corrector block is frozen or disabled.

ADC31RF80 D058_SBAS747.gif Figure 268. Offset Corrector Block Frozen at Room Temperature
ADC31RF80 D060_SBAS747.gif Figure 269. Offset Corrector Block Disabled

Typical Application

The ADC31RF80 is designed for wideband receiver applications demanding high dynamic range over a large input frequency range. Figure 270 shows a typical schematic for an ac-coupled receiver.

Decoupling capacitors with low ESL are recommended to be placed as close as possible at the pins indicated in Figure 270. Additional capacitors can be placed on the remaining power pins.

ADC31RF80 ac_cpld_rcvr_sbas860.gif Figure 270. Typical Application Implementation Diagram

Design Requirements

Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. To ensure good amplitude and phase balance at the analog inputs, transformers (such as TC1-1-13 and TC1-1-43) can be used from the dc to 1000-MHz range and from the 1000-MHz to 4-GHz range of input frequencies, respectively. When designing the driving circuits, the ADC input impedance (or SDD11) must be considered.

By using the simple drive circuit of Figure 271, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

ADC31RF80 ai_input_drive_cir_sbas860.gif Figure 271. Input Drive Circuit

Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin, as shown in Figure 271, is recommended to damp out ringing caused by package parasitics.

Application Curves

Figure 272 and Figure 273 show the typical performance at 100 MHz and 1780 MHz, respectively.

ADC31RF80 D001_SBAS747.gif
SNR = 61.8 dBFS, SINAD = 61.2 dBFS,
HD2 = 71 dBc, HD3 = 75 dBc, SFDR = 71 dBc,
THD = 68 dBc, IL spur = 77 dBc, worst spur = 73 dBc
Figure 272. FFT for 100-MHz Input Frequency
ADC31RF80 D003_SBAS747.gif
SNR = 57.9 dBFS, SINAD = 57.1 dBFS,
HD2 = 63 dBc, HD3 = 66 dBc, SFDR = 63 dBc,
THD = 60 dBc, IL spur = 79 dBc, worst spur = 77 dBc
Figure 273. FFT for 1780-MHz Input Frequency