8.2.2 Detailed Design Procedure

Digital outputs consist of the 1.8 V CMOS signals D0-D13, DRDY and OVR.

The ADC14155 has 16 CMOS compatible data output pins: 14 data output bits corresponding to the converted input value, a data ready (DRDY) signal that should be used to capture the output data and an over-range indicator (OVR) which is set high when the sample amplitude exceeds the 14-bit conversion range. Valid data is present at these outputs while the PD pin is low.

Data should be captured and latched with the rising edge of the DRDY signal. Depending on the setup and hold time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the DRDY signal can be used to latch the data. Generally, rising-edge capture would maximize setup time with minimal hold time; while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the ASIC. Refer to the ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics table.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows through V_DR and DRGND. These large charging current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 5 pF/pin will cause t_OD to increase, reducing the setup and hold time of the ADC output data. The result could be an apparent reduction in dynamic performance.

To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can be done by using a programmable logic device (PLD) such as the LC4032V-25TN48C to level translate the ADC output data from 1.8 V to 3.3 V for use by any other circuitry. Only one load should be connected to each output pin. Additionally, inserting series resistors of about 22 Ω at the digital outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 24.