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SN74AUP2G14

現行

具施密特觸發器輸入的 2 通道 0.8-V 至 3.6-V 低功耗逆變器

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產品規格表

SN74AUP2G14

現行
產品規格表 立即訂購

產品詳細資料

Technology family AUP Number of channels 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AUP Number of channels 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) DSBGA (YFP) 6 1.4000000000000001 mm² (— mm × — mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm)
  • Available in the Texas Instruments NanoStar™ package
  • Low static-power consumption (ICC = 0.9µA maximum)
  • Low dynamic-power consumption (Cpd = 4.3pF typical at 3.3V)
  • Low input capacitance (Ci = 1.5pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Wide operating VCC range of 0.8V to 3.6V
  • Optimized for 3.3V operation
  • 3.6V I/O tolerant to support mixed-mode signal Operation
  • tpd = 4.3ns maximum at 3.3V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100mA Per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)
  • Available in the Texas Instruments NanoStar™ package
  • Low static-power consumption (ICC = 0.9µA maximum)
  • Low dynamic-power consumption (Cpd = 4.3pF typical at 3.3V)
  • Low input capacitance (Ci = 1.5pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Wide operating VCC range of 0.8V to 3.6V
  • Optimized for 3.3V operation
  • 3.6V I/O tolerant to support mixed-mode signal Operation
  • tpd = 4.3ns maximum at 3.3V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100mA Per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8V to 3.6V, resulting in increased battery life (see Figure 5-1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 5-2).

The SN74AUP2G14 contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8V to 3.6V, resulting in increased battery life (see Figure 5-1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 5-2).

The SN74AUP2G14 contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AUP2G14 Low-Power Dual Schmitt-Trigger Inverter datasheet (Rev. D) PDF | HTML 2025/6/1
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 2025/4/17

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模擬型號

SN74AUP2G14 Behavioral SPICE Model

SCEM674.ZIP (7 KB) - PSpice 模型
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USON (DRY) 6 Ultra Librarian
DSBGA (YFP) 6 Ultra Librarian
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