OMAP-L137

現行

低功耗 C674x 浮點 DSP + Arm9 處理器 - 最高 456MHz

立即訂購

產品規格表

document-pdfAcrobat OMAP-L137 Low-Power Applications Processor datasheet (Rev. G) (英文) PDF | HTML

使用指南

document-pdfAcrobat
OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) (英文)

OMAP-L137

現行

產品規格表

立即訂購

產品詳細資料

CPU

1 Arm9

Frequency (MHz)

456

Coprocessors

C674x DSP

Display type

1 LCD

Protocols

Ethernet

Hardware accelerators

Industrial communications subsystem, Programable real-time unit

Operating system

Linux, RTOS

Security

Device attestation & anti-counterfeit, Secure storage

Rating

Catalog

Power supply solution

TPS65910

Operating temperature range (°C)

-40 to 125

CPU

1 Arm9

Frequency (MHz)

456

Coprocessors

C674x DSP

Display type

1 LCD

Protocols

Ethernet

Hardware accelerators

Industrial communications subsystem, Programable real-time unit

Operating system

Linux, RTOS

Security

Device attestation & anti-counterfeit, Secure storage

Rating

Catalog

Power supply solution

TPS65910

Operating temperature range (°C)

-40 to 125

PBGA (ZKB)

256

289 mm² (17 mm × 17 mm)

Software Support
- TI DSP/BIOS
- Chip Support Library and DSP Library
Dual Core SoC
- 375- and 456-MHz ARM926EJ-S RISC MPU
- 375- and 456-MHz C674x VLIW DSP
ARM926EJ-S Core
- 32-Bit and 16-Bit (Thumb®) Instructions
- DSP Instruction Extensions
- Single Cycle MAC
- ARM® Jazelle® Technology
- Embedded ICE-RT™ for Real-Time Debug
ARM9™ Memory Architecture
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
Commercial, Industrial, Extended, or Automotive Temperature

Software Support
- TI DSP/BIOS
- Chip Support Library and DSP Library
Dual Core SoC
- 375- and 456-MHz ARM926EJ-S RISC MPU
- 375- and 456-MHz C674x VLIW DSP
ARM926EJ-S Core
- 32-Bit and 16-Bit (Thumb®) Instructions
- DSP Instruction Extensions
- Single Cycle MAC
- ARM® Jazelle® Technology
- Embedded ICE-RT™ for Real-Time Debug
ARM9™ Memory Architecture
- 16KB of Instruction Cache
- 16KB of Data Cache
- 8KB of RAM (Vector Table)
- 64KB of ROM
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- Up to 3648 MIPS and 2736 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 256KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
128KB of RAM Shared Memory
3.3-V LVCMOS I/Os (Except for USB Interfaces)
Two External Memory Interfaces:
- EMIFA
  - NOR (8- or 16-Bit-Wide Data)
  - NAND (8- or 16-Bit-Wide Data)
  - 16-Bit SDRAM with 128-MB Address Space
- EMIFB
  - 32-Bit or 16-Bit SDRAM with 256-MB Address Space
Three Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- Autoflow Control Signals (CTS, RTS) on UART0 Only
- 16-Byte FIFO
- 16x or 13x Oversampling Option
LCD Controller
Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Realtime Unit (PRU) Cores
  - 32-Bit Load and Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled via Software to Save Power
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
USB 1.1 OHCI (Host) with Integrated PHY (USB1)
USB 2.0 OTG Port with Integrated PHY (USB0)
- USB 2.0 High- and Full-Speed Client
- USB 2.0 High-, Full-, and Low-Speed Host
- End Point 0 (Control)
- End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
Three Multichannel Audio Serial Ports (McASPs):
- Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capable (McASP2)
- FIFO Buffers for Transmit and Receive
10/100 Mbps Ethernet MAC (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Enhanced Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
Commercial, Industrial, Extended, or Automotive Temperature

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors.

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TI 提供有限的設計支援

使用此產品的現有專案具備有限的 TI 設計支援。若有提供，您可在此頁面找到相關資訊、工具和軟體。使用此產品的現有設計具備有限的 TI 設計支援。在 TI E2E™ 支援論壇中申請有限的設計支援。

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重要文件	類型	標題	格式選項	日期
*	資料表	OMAP-L137 Low-Power Applications Processor datasheet (Rev. G)	PDF \| HTML	2014/6/17
*	使用指南	OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D)		2016/9/21
*	勘誤表	OMAP-L137 C6000 DSP+ARM Processor Errata (Silicon Revs 3.0, 2.1, 2.0, 1.1 & 1.0) (Rev. I)		2014/6/17
	使用指南	ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z)	PDF \| HTML	2023/3/30
	使用指南	ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W)	PDF \| HTML	2023/3/30
	應用說明	High-Speed Interface Layout Guidelines (Rev. J)	PDF \| HTML	2023/2/24
	使用指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020/6/1
	應用說明	General Hardware Design/BGA PCB Design/BGA	PDF \| HTML	2019/2/22
	應用說明	OMAP-L13x / C674x / AM1x schematic review guidelines	PDF \| HTML	2019/2/14
	應用說明	McASP Design Guide - Tips, Tricks, and Practical Examples		2019/1/10
	白皮書	Designing professional audio mixers for every scenario		2018/6/28
	使用指南	TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)		2012/8/21
	使用指南	TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)		2012/8/21
	應用說明	Using the OMAP-L1x7 Bootloader (Rev. G)		2012/6/1
	應用說明	Powering the OMAP-L132/OMAP-L137/OMAP-L138 Processor with the TPS650061		2012/4/13
	白皮書	MityDSP®-L138F Software Defined Radio Using uPP Data Transfer (Rev. A)		2012/2/2
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)		2011/9/14
	白皮書	OpenCV on TI’s DSP+ARM®		2011/7/27
	白皮書	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		2011/5/19
	應用說明	Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B)		2010/8/26
	使用指南	TMS320C674x DSP Megamodule Reference Guide (Rev. A)		2010/8/3
	使用指南	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)		2010/7/30
	應用說明	OMAP-L137 Power Consumption Summary		2010/6/30
	應用說明	Power Solution using a Dual DCDC Converter and a LDO (Rev. A)		2010/3/25
	應用說明	Power Solution using LDO's (Rev. A)		2010/3/25
	更多文件說明	OMAP-L1x Software Solutions Diagram (Rev. B)		2009/12/7
	應用說明	Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB		2009/11/25
	應用說明	OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A)		2009/9/26
	應用說明	OMAP-L137 Complementary Products		2009/9/23
	白皮書	Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core		2009/6/24
	應用說明	TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing		2009/3/12
	應用說明	TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing		2009/3/12
	應用說明	TMS320C674x/OMAP-L1x USB Compliance Checklist		2009/3/12
	應用說明	OMAP-L137 Technical Brief (Rev. B)		2009/2/18
	使用指南	TMS320C674x DSP Cache User's Guide (Rev. A)		2009/2/11

設計與開發

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開發板

TMDSOSKL137 — OMAP-L137/TMS320C6747 浮點入門套件

與 Spectrum Digital Inc. 聯合開發的 OMAP-L137/TMS320C6747 浮點入門套件是低成本開發平台，設計目的在於加快基於 TI OMAP-L13x 應用處理器和 TMS320C674x 定點/浮點 DSP (TMS320C6747、TMS320C6745 和 TMS320C6743) 的高精密度應用開發速度。該套件使用 USB 通訊來真正發揮即插即用功能。資深和新進設計人員都可以使用該入門套件的全方位 Code Composer Studio™ 整合開發環境 (IDE) 和 eXpressDSP™ 軟體 (包含 DSP/BIOS™ 核心) (...)

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偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-OMAPL137 — TI-RTOS Processor SDK for OMAP-L137 and C6747, C6745, C6743 (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

OMAP-L137 的處理器 SDK 包含對 TI-RTOS 作業系統的支援。

RTOS 主要特點：

TI RTOS 核心，這是一套適用於 TI 裝置的輕量即時嵌入式作業系統
晶片支援函式庫、驅動程式和基礎電路板支援公用程式
最佳化 C674x (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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啟動

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作業系統 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)

從：Mentor Graphics Corporation

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驅動程式或資料庫

MATHLIB — 用於浮點裝置的 DSP 數學函式庫

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)

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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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驅動程式或資料庫

SPRC265 — TMS320C6000 DSP 函式庫 (DSPLIB)

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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驅動程式或資料庫

WIND-3P-VXWORKS-LINUX-OS — Wind River 處理器 VxWorks 和 Linux 作業系統

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)

從：Wind River Systems

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造訪合作夥伴網站

軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

從：Adaptive Digital Technologies, Inc.

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軟體轉碼器

AURO-3P-3DENGINE — Auro Technologies Auro 轉碼器和 Auro-Matic 軟體

Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.

從：Auro Technologies N.V.

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