LP2997

現行

DDR-II 終端穩壓器

產品詳細資料

Product type DDR Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.822 Vout (max) (V) 0.887 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR2
Product type DDR Vin (min) (V) 1.8 Vin (max) (V) 5.5 Vout (min) (V) 0.822 Vout (max) (V) 0.887 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 DDR memory type DDR2
HSOIC (DDA) 8 29.4 mm² (4.9 mm × 6 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

All trademarks are the property of their respective owners.

  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

All trademarks are the property of their respective owners.

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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LP2996-N 現行 適用 DDR2 且具關閉接腳的 1.5A DDR 終端穩壓器 DDR-I And DDR-II Linear Termination Regulator

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LP2997 DDR-II Termination Regulator datasheet (Rev. F) 2013/4/4
應用說明 Limiting DDR Termination Regulators’ Inrush Current 2016/8/23
應用說明 AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) 2013/5/6

設計與開發

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模擬型號

LP2997 PSpice Transient Model

SNVMAH7.ZIP (70 KB) - PSpice 模型
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模擬型號

LP2997 Unencrypted PSpice Transient Model

SNVMAH8.ZIP (4 KB) - PSpice 模型
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參考設計

TIDA-010011 — 用於保護繼電器處理器模組的高效電源供應架構參考設計

此參考設計展示各種電源架構,可為需要 >1A 負載電流和高效率的應用處理器模組產生多重電壓軌。所需的電源是使用來自背板的 5、12 或 24-V DC 輸入所產生。電源供應器是使用配備整合式 FET 的 DC-DC 轉換器,以及具尺寸整合式電感器的電源模組所產生。此設計採用 HotRod™ 封裝類型,適合需要低 EMI 的應用。此外也最適合設計時間有限的應用。其他功能包括 DDR 終端穩壓器、輸入電源 OR-ing、電壓序列、用於過載保護的 eFuse,以及電壓和負載電流監控。此設計可搭配處理器、數位訊號處理器以及現場可編程邏輯閘陣列使用。已通過輻射發射測試,符合 A 類和 B 要求的 (...)
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