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TS5N412

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10V、2:1 (SPDT)、四通道模拟开关

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TS5N412

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产品详情

Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 3 CON (typ) (pF) 80 Bandwidth (MHz) 25 Operating temperature range (°C) -40 to 85 Features Powered-off protection Input/output continuous current (max) (A) 0.1 Rating Catalog Drain supply voltage (max) (V) 5.25
Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5 Protocols Analog Ron (typ) (Ω) 3 CON (typ) (pF) 80 Bandwidth (MHz) 25 Operating temperature range (°C) -40 to 85 Features Powered-off protection Input/output continuous current (max) (A) 0.1 Rating Catalog Drain supply voltage (max) (V) 5.25
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SSOP (DBQ) 16 29.4 mm² (4.9 mm × 6 mm)
  • Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Typ)
  • 0- to 10-V Switching on Data I/O Ports
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 20 pF Max, B Port)
  • VCC Operating Range From 4.75 V to 5.25 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications
  • APPLICATIONS
    • PCI Interface
    • Differential Signal Interface
    • Memory Interleaving
    • Bus Isolation
    • Low-Distortion Signal Gating
  • Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Typ)
  • 0- to 10-V Switching on Data I/O Ports
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 20 pF Max, B Port)
  • VCC Operating Range From 4.75 V to 5.25 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications
  • APPLICATIONS
    • PCI Interface
    • Differential Signal Interface
    • Memory Interleaving
    • Bus Isolation
    • Low-Distortion Signal Gating

The TS5N412 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the TS5N412 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The TS5N412 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single output-enable (OE) input. The select (S) inputs control the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The TS5N412 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the TS5N412 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The TS5N412 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single output-enable (OE) input. The select (S) inputs control the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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* 数据表 TS5N412 数据表 2005-7-28

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