TS2PCIE412

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4 通道 PCIe 8:16 多路复用器和多路解复用器无源 FET 开关

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数据表

document-pdfAcrobat 4-Channel 8:16 Multiplexer/Demultiplexer PCI Express Switch 数据表 (Rev. C) (英语)

TS2PCIE412

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产品详情

Protocols

PCIe1, PCIe2

Number of channels

4

Bandwidth (MHz)

2100

Operating temperature range (°C)

-40 to 85

Ron (max) (mΩ)

18000

Rating

Catalog

Protocols

PCIe1, PCIe2

Number of channels

4

Bandwidth (MHz)

2100

Operating temperature range (°C)

-40 to 85

Ron (max) (mΩ)

18000

Rating

Catalog

WQFN (RUA)

42

31.5 mm² (9 mm × 3.5 mm)

Compatible With PCI Express (PCIe) Standard
Wide Bandwidth of over 3 Gbps
Low Crosstalk (X_TALK = –32 dB Typ at 1.25 GHz)
O_IRR = –36.3 dB Typical at 1.25 GHz
Low Bit-to-Bit Skew (t_sk(O) = 0.06 ns Typical)
V_DD Operating Range: 1.5 V to 2 V
I_offSupports Partial Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
APPLICATIONS
- PCIe Bus Multiplexing and Expansion
- Routing PCI Express Data and/or Display Port Signals
- Notebook PCs
- Desktop PCs
- Servers/Storage Area Networks

All other trademarks are the property of their respective owners.

Compatible With PCI Express (PCIe) Standard
Wide Bandwidth of over 3 Gbps
Low Crosstalk (X_TALK = –32 dB Typ at 1.25 GHz)
O_IRR = –36.3 dB Typical at 1.25 GHz
Low Bit-to-Bit Skew (t_sk(O) = 0.06 ns Typical)
V_DD Operating Range: 1.5 V to 2 V
I_offSupports Partial Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
APPLICATIONS
- PCIe Bus Multiplexing and Expansion
- Routing PCI Express Data and/or Display Port Signals
- Notebook PCs
- Desktop PCs
- Servers/Storage Area Networks

All other trademarks are the property of their respective owners.

The TS2PCIE412 is a 4-channel PCIe 2:1 multiplexer/demultiplexer switch that can be used to route one PCIe data lane between two possible destinations or two PCIe data lanes to one destination. Each channel consists of differential pairs of receive (RX) and transmit (TX) signals and operates at a signal-processing bandwidth speed, which supports the PCIe standard of 2.5 Gbps. The device is controlled with one select input (SEL) pin, where SEL controls the data path of the multiplexer/demultiplexer and can be connected to any GPIO in the system. The unselected channel is set in a high-impedance state.

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