TLC3541
- 200-KSPS Sampling Rate
- Built-In Conversion Clock
- INL: ±1 LSB Max
DNL: ±1 LSB Max - SINAD = 81.5 dB, SFDR = 95 dB
THD = 94 dB at 15 kHz fin, 200 KSPS - SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz
- Single 5-V Supply
- Rail-to-Rail Analog Input With 500 kHz BW
- Two Input Options Available:
- TLC3541 – Single Channel Input
- TLC3545 – Single Channel, Pseudo-Differential Input
- (TLC3541) Optimized DSP Interface – Requires FS Input Only
- Low Power With Auto-Power Down
- Operating Current: 3.5 mA
- Auto-Powerdown Current: 5 uA
- Pin Compatible 12-/14-/16-Bit Family in 8-Pin SOIC and MSOP Packages
- APPLICATIONS
- ATE System
- Industrial Process Control
- Measurement
- Motor Control
The TLC3541 and TLC3545 are a family of high performance, 14-bit, low power, miniature CMOS analog-to-digital converters (ADCs). These devices operate from a single 5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. All of these devices have a chip select (CS)\, serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate the start of a serial data frame on either pin 1 (CS)\ or pin 7 (FS) for the TLC3541. The TLC3545 ADC connects to the DSP via pin 1 only (CS)\.
The TLC3541 and TLC3545 are designed to operate with low power consumption. The power saving feature is further enhanced with an auto-power down mode. This product family features a high-speed serial link to modern host processors with an external SCLK up to 15 MHz. Both families use a built-in oscillator as the conversion clock, providing a 2.67 us maximum conversion time.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 5-V, Low Power, 14-Bit, 200 KSPS, Serial ADC with Auto-Power Down 数据表 | 2001-5-23 | |||
| 电子书 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015-5-21 | ||||
| 应用手册 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011-3-17 |
设计与开发
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5-6KINTERFACE — 5-6K 接口式评估模块
接口板由两个信号调节站点、两个串行 EVM 站点和一个并行 EVM 站点组成。无论接口类型如何，与 5-6K 接口板兼容的所有 EVM 都具有标准模拟接口和标准电源连接器。三位螺丝端子 J1 和 J2 以及两位螺丝端子 J6、J8、J9 和 J11 可接入连接至所有站点的公共电源总线
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| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
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