SN74LVC861A
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.4 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
This 10-bit bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC861A is designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic levels at the output-enable (OEAB\ and OEBA)\ inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | 10-Bit Bus Transceiver With 3-State Outputs 数据表 (Rev. I) | 2003-7-31 |
设计与开发
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14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |
| SSOP (DB) | 24 | Ultra Librarian |
| TSSOP (PW) | 24 | Ultra Librarian |
| TVSOP (DGV) | 24 | Ultra Librarian |