SN74LVC2G125-Q1
- Qualified for Automotive Applications
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.3 ns at 3.3 V
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | Dual Bus Buffer Gate With 3-State Output 数据表 (Rev. C) | 2011-3-31 | |||
| 更多文献资料 | 汽车逻辑器件 | 英语版 | 2014-2-5 |
设计与开发
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评估板
5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑评估模块
灵活的 EVM 设计用于支持具有 5 至 8 引脚数且采用 DCK、DCT、DCU、DRL 或 DBV 封装的任何器件。
用户指南:
PDF
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SSOP (DCT) | 8 | Ultra Librarian |
| VSSOP (DCU) | 8 | Ultra Librarian |