主页 逻辑和电压转换 逻辑门 与门
主页
逻辑和电压转换
逻辑门
与门

SN74LVC2G08-EP

正在供货

增强型产品、2 通道、2 输入、1.65V 至 5.5V 32mA 驱动强度与门

立即订购
数据表

SN74LVC2G08-EP

正在供货
立即订购

产品详情

Technology family LVC Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LVC Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm)
  • Controlled Baseline
    • One Assembly
    • One Test Site
    • One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.7 ns at 3.3 V
  • Low Power Consumption, 10 µA Max ICC
  • ±24 mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly
    • One Test Site
    • One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.7 ns at 3.3 V
  • Low Power Consumption, 10 µA Max ICC
  • ±24 mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G08 performs the Boolean function Y = A • or Y = A\ + B\ in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G08 performs the Boolean function Y = A • or Y = A\ + B\ in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter 查找其他 与门
下载 观看带字幕的视频 视频

技术文档

未找到结果。请清除搜索并重试。
查看全部 3
顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Dual 2-Input Positive-AND Gate 数据表 2007-9-12
* 辐射与可靠性报告 SN74LVC2G08MDCUREP Reliability Report 2013-4-24
* VID SN74LVC2G08-EP VID V6207631 2016-6-21

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

封装 引脚 CAD 符号、封装和 3D 模型
VSSOP (DCU) 8 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

订购和质量

支持和培训

可获得 TI 工程师技术支持的 TI E2E™ 论坛

查看全部论坛主题 查看英文版全部论坛主题

所有内容均由 TI 和社区贡献者按“原样”提供，并不构成 TI 规范。请参阅使用条款。

如果您对质量、包装或订购 TI 产品有疑问，请参阅 TI 支持。​​​​​​​​​​​​​​

视频