SN74LVC1G374

正在供货

具有三态输出的单路 D 级触发器

立即订购

数据表

document-pdfAcrobat SN74LVC1G374 数据表 (Rev. C) (英语)

SN74LVC1G374

正在供货

立即订购

产品详情

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

DSBGA (YZP)

6

2.1875 mm² (— mm × — mm)

SOT-23 (DBV)

6

8.12 mm² (2.9 mm × 2.8 mm)

SOT-SC70 (DCK)

6

4.2 mm² (2 mm × 2.1 mm)

Available in the Texas Instruments NanoStar and NanoFree Packages
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 4 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoStar and NanoFree Packages
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 4 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This single D-type latch is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.

A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.