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SN74LVC1G175-EP

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具有异步清零功能的单通道 D 型触发器（增强型产品）

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SN74LVC1G175-EP

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产品详情

Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Number of channels 1 Technology family LVC Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 150 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Military (–55°C/125°C)
      Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) Additional temperature ranges available - contact factory
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Military (–55°C/125°C)
      Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) Additional temperature ranges available - contact factory

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 SN74LVC1G175-EP 数据表 (Rev. A) 2010-12-14
* 辐射与可靠性报告 CLVC1G175MDCKREP Reliability Report 2011-11-30
* VID SN74LVC1G175-EP VID V6206633 2016-6-21
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022-12-15

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封装 引脚 CAD 符号、封装和 3D 模型
SOT-SC70 (DCK) 6 Ultra Librarian
适用于评估类项目的 TI 标准条款与条件。

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