SN74LVC16244A-Q1

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具有三态输出的汽车类 16 通道、1.65V 至 3.6V 缓冲器

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数据表

document-pdfAcrobat SN74LVC16244A-Q1 数据表 (英语)

SN74LVC16244A-Q1

正在供货

数据表

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产品详情

Technology family

LVC

Number of channels

16

IOL (max) (mA)

24

Supply current (max) (µA)

20

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Automotive

Operating temperature range (°C)

-40 to 85

Technology family

LVC

Number of channels

16

IOL (max) (mA)

24

Supply current (max) (µA)

20

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Automotive

Operating temperature range (°C)

-40 to 85

TSSOP (DGG)

48

101.25 mm² (12.5 mm × 8.1 mm)

Qualification in Accordance With AEC-Q100⁽¹⁾
Qualified for Automotive Applications
Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval
Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.1 ns at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Signal Operation On All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Latch-Up Performance Exceeds 100 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Contact factory for details. Q100 qualification data available on request.
Widebus is a trademark of Texas Instruments.

Qualification in Accordance With AEC-Q100⁽¹⁾
Qualified for Automotive Applications
Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval
Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.1 ns at 3.3 V
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Signal Operation On All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Latch-Up Performance Exceeds 100 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Contact factory for details. Q100 qualification data available on request.
Widebus is a trademark of Texas Instruments.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 16-bit buffer/driver is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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