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SN74LS697

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具有输出寄存器和多路复用三态输出的同步 4 位加/减二进制计数器

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SN74LS697

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产品详情

Function Counter Bits (#) 4 Technology family LS Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Function Counter Bits (#) 4 Technology family LS Input type Bipolar Output type 3-State Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm)
  • 4-Bit Counters/Registers
  • Multiplexed Outputs for Counter or Latched Data
  • 3-State Outputs Drive Bus Lines Directly
  • 'LS696 … Decade Counter, Direct Clear'LS697…Binary Counter, Direct Clear'LS699…Binary Counter, Synchronous Clear

 
  • 4-Bit Counters/Registers
  • Multiplexed Outputs for Counter or Latched Data
  • 3-State Outputs Drive Bus Lines Directly
  • 'LS696 … Decade Counter, Direct Clear'LS697…Binary Counter, Direct Clear'LS699…Binary Counter, Synchronous Clear

 

These low-power Schottky LSI devices incorporate synchronous up/down counters, four-bit D-type registers, and quadruple two-line to one-line multiplexers with three state outputs in a single 20-pin package. The up/down counters are programmable from the data inputs and feature enable P\ and enable T\ and a ripple-carry output for easy expansion. The register/counter select input R/C\, selects the counter when low and the register when high for the three-state outputs, QA, QB, QC, and QD. These outputs are rated at 12 and 24 milliamperes (54LS/74LS) for good bus driving performance.

Both the counter CCK and register clock RCK are positive-edge triggered. The counter clear CCLR\ is active low and is asynchronous on the 'LS696 and 'LS697, synchronous on the 'LS699. Loading of the counter is accomplished when LOAD\ is taken low and a positive transition occurs on the counter clock CCK.

Expansion is easily accomplished by connecting RCO\ of the first stage to ENT\ of the second stage, etc. All ENP\ inputs can be tied common and used as a master enable or disable control.

 

These low-power Schottky LSI devices incorporate synchronous up/down counters, four-bit D-type registers, and quadruple two-line to one-line multiplexers with three state outputs in a single 20-pin package. The up/down counters are programmable from the data inputs and feature enable P\ and enable T\ and a ripple-carry output for easy expansion. The register/counter select input R/C\, selects the counter when low and the register when high for the three-state outputs, QA, QB, QC, and QD. These outputs are rated at 12 and 24 milliamperes (54LS/74LS) for good bus driving performance.

Both the counter CCK and register clock RCK are positive-edge triggered. The counter clear CCLR\ is active low and is asynchronous on the 'LS696 and 'LS697, synchronous on the 'LS699. Loading of the counter is accomplished when LOAD\ is taken low and a positive transition occurs on the counter clock CCK.

Expansion is easily accomplished by connecting RCO\ of the first stage to ENT\ of the second stage, etc. All ENP\ inputs can be tied common and used as a master enable or disable control.

 
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* 数据表 Synchronous Up/Down Counters With Output Reg. And Multiplexed 3-State Outputs 数据表 1988-3-1

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