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JK 触发器

SN74LS112A

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具有清零和预置功能的双通道负边沿触发式 J-K 触发器

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SN74LS112A

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产品详情

Number of channels 2 Technology family LS Input type TTL Output type Push-Pull Clock frequency (MHz) 30 Supply current (max) (µA) 6000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Clear, High speed (tpd 10-50ns), Negative edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Technology family LS Input type TTL Output type Push-Pull Clock frequency (MHz) 30 Supply current (max) (µA) 6000 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Features Clear, High speed (tpd 10-50ns), Negative edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
  • Fully Buffered to Offer Maximum Isolation from External Disturbance
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 
  • Fully Buffered to Offer Maximum Isolation from External Disturbance
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

 

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

 
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* 数据表 Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 数据表 1988-3-1

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