SN74HCT540
- Operating Voltage Range of 4.5 V to 5.5 V
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 12 ns
- ±6-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Inputs Are TTL-Voltage Compatible
- High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
- Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
These octal buffers and line drivers are designed to have the performance of the ’HCT240 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.
The 3-state control gate is a 2-input NOR. If either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state. The ’HCT540 devices provide inverted data at the outputs.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SN54HCT540, SN74HCT540 数据表 (Rev. C) | 2003-3-18 |
设计与开发
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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| SOIC (DW) | 20 | Ultra Librarian |
| PDIP (N) | 20 | Ultra Librarian |