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数字多路信号分离器和解码器

SN74HCS237-Q1

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具有地址锁存器的汽车类高速 CMOS 逻辑 3 线至 8 线解码器/多路信号分离器

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SN74HCS237-Q1

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产品详情

Technology family HCS Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 2
Technology family HCS Number of channels 1 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 2
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm)
  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1: –40°C to +125°C, TA
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classifcation Level C6
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1: –40°C to +125°C, TA
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classifcation Level C6
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V

The SN74HCS237-Q1 is a three to eight decoder with latched address inputs, one standard output strobe (G0), and one active low output strobe (G 1). When the latch enable (LE) input is low, the device acts as a standard three to eight decoder. When the latch enable (LE) input is high, the address latch retains its previous state. When the outputs are gated by either strobe input, they are all forced into the low state. When the outputs are not disabled by one or both of the strobe inputs, only the selected output is high while all others are low.

The SN74HCS237-Q1 is a three to eight decoder with latched address inputs, one standard output strobe (G0), and one active low output strobe (G 1). When the latch enable (LE) input is low, the device acts as a standard three to eight decoder. When the latch enable (LE) input is high, the address latch retains its previous state. When the outputs are gated by either strobe input, they are all forced into the low state. When the outputs are not disabled by one or both of the strobe inputs, only the selected output is high while all others are low.
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* 数据表 SN74HCS237-Q1 Automotive Qualified 3- to 8-Line Decoder/Demultiplexer with Address Latches and Schmitt-Trigger Inputs 数据表 (Rev. A) PDF | HTML 2021-6-16

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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 设计用于支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

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SN74HCS237 IBIS Model

SCLM322.ZIP (249 KB) - IBIS 模型
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TSSOP (PW) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
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